An arc fault circuit interrupter (AFCI) protects against electrical fires by detecting the high-frequency broadband noise (typically 10 kHz to 100 kHz) generated by arcing faults, which rides on top of the standard 50/60 Hz AC waveform. To safely capture and analyze these microsecond-level arc signatures with a microcontroller, you cannot simply wire a shunt resistor to an analog pin. You need a galvanically isolated current transformer feeding an active high-pass filter into the ESP32 ADC. This guide walks through the exact analog front-end topology, component values, and failure modes required to build a bench-top AFCI signature analyzer.

⚠️ HIGH VOLTAGE SAFETY WARNING: Never breadboard or probe live 120V/240V mains circuits directly. The topology below uses a current transformer for isolation, but an open-circuit fault on the secondary side can generate lethal voltages. Always perform initial validation using a low-voltage AC source (like a 12V doorbell transformer) or a function generator before moving to a controlled mains test bench.

Topology & Node Map for High-Frequency Arc Detection

The core challenge of arc fault detection is dynamic range. A 15A nominal load produces a massive 60 Hz fundamental signal, while the actual series arc fault generates millivolt-level high-frequency noise. If you feed both directly into the ESP32's 12-bit ADC, the 60 Hz wave will saturate the input, and the arc noise will be lost in the quantization floor.

Our topology solves this by stripping away the fundamental frequency before the signal hits the microcontroller. Here is the signal path:

  • Node A (Primary AC Line): The mains hot wire passes through the core of the current transformer. No electrical connection is made.
  • Node B (CT Secondary / Burden): The secondary leads of the current transformer terminate across a burden resistor, converting the induced current into a proportional voltage.
  • Node C (High-Pass Filter Output): A passive RC network blocks the 60 Hz fundamental and passes frequencies above 10 kHz.
  • Node D (Op-Amp Output): A rail-to-rail operational amplifier boosts the millivolt-level high-frequency noise to a 0–3.3V swing.
  • Node E (ESP32 ADC Input): The amplified noise signature feeds into GPIO 34 (ADC1_CH6) for high-speed sampling.

Why This Topology Over a Shunt Resistor?

The alternative approach is using a low-value shunt resistor (e.g., 10mΩ) in series with the load, followed by a differential amplifier. While shunts offer better DC/low-frequency accuracy, they require breaking the mains circuit and lack galvanic isolation, meaning a component failure could expose your 3.3V microcontroller—and you—to 120V AC. The current transformer (CT) topology guarantees isolation. Furthermore, by placing the high-pass filter before the active gain stage, we prevent the op-amp from slewing-rate limiting on the massive 60 Hz swing, preserving its bandwidth for the high-frequency arc noise.

Component Selection & Design Walkthrough

To build this on a breadboard, we need components that operate cleanly on a single 3.3V supply and handle the required bandwidth. Here are the exact values for a 10 kHz cutoff frequency and a gain of 11.

  • Current Transformer (CT): YHDC SCT-013-000 (100A:50mA ratio). This is a split-core, non-invasive sensor.
  • Burden Resistor (R1): 33Ω (Node A to Node B). At 100A primary, this yields 1.65V RMS. For arc noise (mA levels), it provides a safe baseline without clipping.
  • High-Pass Capacitor (C1): 10nF metallized polypropylene film capacitor. (Avoid ceramic X7R here; they exhibit piezoelectric microphonics that mimic arc noise).
  • High-Pass Resistor (R2): 1.6kΩ to ground. This sets the RC cutoff: f = 1 / (2π × 10nF × 1.6kΩ) ≈ 9.9 kHz.
  • Operational Amplifier: Microchip MCP6002. It is rail-to-rail I/O, operates at 3.3V, and has a 1 MHz gain-bandwidth product (sufficient for 100 kHz arc noise).
  • Gain Resistors (R3, R4): R3 = 1kΩ (inverting input to GND), R4 = 10kΩ (feedback). Non-inverting gain = 1 + (10k/1k) = 11.

Behavior Matrix: What Changes When Elements Shift

Circuit Element Modification Effect on Arc Fault Detection
Burden Resistor (R1) Increase to 100Ω Increases baseline voltage. Risks clipping the 60 Hz fundamental on the ADC if load exceeds 30A, masking high-frequency noise.
HPF Capacitor (C1) Increase to 100nF Drops cutoff frequency to ~1 kHz. Allows universal motor brush noise (e.g., vacuums, drills) to pass, causing massive false-positive trip rates.
Feedback Resistor (R4) Short circuit (0Ω) Op-amp becomes unity gain. Arc noise drops below the ESP32 ADC noise floor (~10mV), rendering the analyzer blind to series arcs.
CT Core Air gap introduced (poor mating) Drops inductance, altering phase response and attenuating low-amplitude parallel arc signatures.

Breadboard Testing & Failure Mode Analysis

Testing an analog front-end for an arc fault circuit interrupter requires a controlled noise injection. Do not use live mains for your first power-on. Use a function generator set to output a 60 Hz sine wave (1V peak) mixed with a 20 kHz burst (50mV peak) to simulate an arc event.

Step-by-Step Breadboard Verification

  1. Verify the Power Rails: Power the ESP32 and the MCP6002 VCC pin from a clean 3.3V LDO. Measure the rail with a multimeter; it must read 3.30V ± 0.05V. Noise on the 3.3V rail will couple directly into Node D.
  2. Test the High-Pass Filter (Passive): Disconnect the op-amp. Inject a 60 Hz signal into C1. Measure Node C with an oscilloscope. You should see near 0V. Switch the generator to 20 kHz; Node C should pass the signal with minimal attenuation.
  3. Validate Op-Amp Bias: With no AC input, measure Node D. Because we are running on a single 3.3V supply, the non-inverting input must be biased to VCC/2 (1.65V) using a voltage divider. Node D should sit at exactly 1.65V DC.
  4. Inject the Arc Signature: Apply the mixed 60 Hz + 20 kHz signal to Node A (via a step-down transformer or simulated CT primary). Probe Node E. You should see a clean 20 kHz waveform centered on 1.65V, with the 60 Hz wave completely rejected.
  5. Sample with the ESP32: Configure the ESP32 Oneshot ADC API to sample GPIO 34 at 200 kS/s. Run an FFT in firmware to verify the 20 kHz bin spikes while the 60 Hz bin remains at the noise floor.

Extremes: What Breaks at the Limits?

Understanding failure modes is critical when designing safety circuits. NEC Article 210.12 mandates strict reliability for AFCI devices, meaning your analyzer must anticipate hardware faults.

  • Open Circuit on Node B (CT Secondary): Catastrophic Failure. If the burden resistor R1 fails open or a breadboard jumper pops out while Node A is energized, the current transformer acts as a step-up transformer. The secondary voltage will spike into the thousands of volts, arcing across the breadboard, destroying the MCP6002, and posing a severe shock hazard. Always use a Zener diode (e.g., 5.1V) clamped across Node B to GND as a failsafe.
  • Short Circuit on C1 (Filter Cap): Functional Failure. If the 10nF capacitor shorts, the 60 Hz fundamental bypasses the high-pass filter and hits the op-amp. The MCP6002 output will slam against the 3.3V and 0V rails at 60 Hz, completely blinding the ESP32 to any high-frequency arc noise.

Frequently Asked Questions

Why does my arc fault circuit interrupter trip when I turn on a vacuum?

This is the most common nuisance trip in residential wiring. Vacuums, corded drills, and older routers use universal motors with carbon brushes. As the brushes commutate against the spinning armature, they create micro-arcs that generate broadband high-frequency noise. To a basic AFCI algorithm, this brush noise looks electrically identical to a dangerous series arc fault in the wall. Modern combination AFCIs use advanced digital signal processing (DSP) to analyze the step-function characteristics and zero-crossing interruptions of the noise, distinguishing the repetitive, predictable pattern of a motor brush from the chaotic, random signature of a degrading wire.

Can a microcontroller replace a commercial arc fault circuit interrupter?

No. While an ESP32 or STM32 can easily sample the waveform and run the FFT algorithms required to detect an arc, a commercial AFCI must meet UL 1699 certification standards. This requires hardware-level fail-safes, specific trip timing (usually clearing the fault within 8 to 10 AC cycles), and guaranteed operation under extreme thermal and electromagnetic interference (EMI) conditions. Software running on a standard RTOS or bare-metal loop cannot guarantee the deterministic microsecond-level response times required by the safety standard, nor can a hobbyist breadboard provide the necessary dielectric isolation and arc-quenching physical design.

What is the difference between an arc fault circuit interrupter and a GFCI?

They protect against entirely different hazards using different physics. A Ground Fault Circuit Interrupter (GFCI) monitors the current imbalance between the hot and neutral wires; if even 4 to 6 milliamps leak to ground (e.g., through a person's body to a wet floor), it trips in milliseconds to prevent lethal electrocution. An arc fault circuit interrupter (AFCI) monitors the high-frequency noise profile of the circuit to detect sparking (arcing) that generates intense localized heat, which causes electrical fires inside walls. A circuit can have a massive, fire-starting arc fault with zero ground leakage, meaning a GFCI will not trip. Conversely, a clean, silent ground fault will trip a GFCI but won't trigger an AFCI. Modern code often requires dual-function (CAFCI/GFCI) breakers that combine both topologies into a single module.