The Anatomy of an Embedded Arc Circuit Interrupter
Commercial arc fault circuit interrupters (AFCIs) use dedicated ASICs to detect the high-frequency broadband noise (typically 10 kHz to 100 kHz) generated by arcing faults, distinguishing it from normal 50/60 Hz mains current and harmless appliance noise. When building an embedded arc circuit interrupter monitor using an ESP32, the microcontroller's ADC is far too slow and noisy to sample raw 100 kHz RF directly while simultaneously managing WiFi stacks and application logic.
The solution is an Analog Front-End (AFE) that isolates the high-frequency arc signature, amplifies it, and converts it into a readable DC envelope. Below is the active high-pass filter and amplifier topology designed specifically for 3.3V embedded systems.
Topology and Node Labels
- Node A (CT_OUT): Secondary output of the current transformer (SCT-013-000).
- Node B (HPF_IN): AC coupling junction. Blocks 60 Hz mains hum, passes HF noise.
- Node C (HPF_OUT): Output of the 2nd-order Sallen-Key High-Pass Filter (U1A).
- Node D (AMP_OUT): Output of the non-inverting gain stage (U1B).
- Node E (ENV_OUT): Hardware envelope detector output, feeding the ESP32 ADC.
Component Selection and Filter Topology Walkthrough
Why use an active Sallen-Key high-pass filter instead of a simple passive RC network? A passive RC filter capable of blocking 60 Hz while passing 10 kHz would require either massive, lossy inductors or it would severely attenuate the microvolt-level arc signatures due to loading effects on the current transformer. The active Sallen-Key topology provides a sharp -40dB/decade roll-off, buffers the CT, and operates cleanly on a single 3.3V rail using a rail-to-rail op-amp like the Microchip MCP6022.
Design Walkthrough: Picking Real Values
Our target cutoff frequency ($f_c$) is 10 kHz to reject 60 Hz fundamental and low-order harmonics, while passing the 10 kHz+ arc noise. We use the unity-gain Sallen-Key high-pass equations:
$f_c = \frac{1}{2 \pi \sqrt{R1 \cdot R2 \cdot C2 \cdot C3}}$
Setting R1 = R2 = 10 kΩ and C2 = C3 = 1.5 nF yields a cutoff frequency of approximately 10.6 kHz.
For the gain stage (U1B), arc signatures at Node C are typically in the 10 mV to 50 mV range. To make this readable by the ESP32's 12-bit ADC (which has a practical resolution floor around 50 mV due to internal noise), we need a gain of roughly 50. Using a feedback resistor (Rf) of 47 kΩ and a ground resistor (Rg) of 1 kΩ gives a non-inverting gain of $1 + (47/1) = 48$.
Behavior Table: Element Variance
| Component | Normal State | What Changes When Value Increases | What Changes When Value Decreases |
|---|---|---|---|
| C1 (Coupling, 100nF) | Blocks 60Hz, passes >1kHz | Cutoff drops, more 60Hz bleed-through | Cutoff rises, attenuates low-end arc noise |
| R1/R2 (Filter, 10kΩ) | Sets 10.6kHz cutoff with C2/C3 | Cutoff frequency drops, phase shift alters | Cutoff frequency rises, op-amp loads heavily |
| Rf (Gain, 47kΩ) | Sets U1B gain to 48 | Gain increases, risk of 3.3V rail clipping | Gain drops, arc signal lost in ESP32 ADC noise |
Failure Modes: What Breaks at the Extremes
When prototyping mains-adjacent sensors, understanding open and short failure modes is critical for both circuit function and physical safety.
The SCT-013-000 is a current-output transformer with no internal burden resistor. Never open-circuit the secondary (Node A) while the primary is under load. An open secondary on a live CT will generate lethal high-voltage spikes that will destroy your op-amp, arc across your breadboard, and pose a severe shock hazard. Always short the CT secondary when not connected to the burden/filter network.
Circuit-Level Extremes
- C1 (Coupling Cap) Shorts: The 60 Hz mains signal (up to 1.65V peak for a 100A load) floods the Sallen-Key filter. U1A will rail-to-rail saturate at 3.3V and 0V. The high-frequency arc signal will be completely masked by the clipping 60 Hz waveform. The ESP32 will read a constant saturated value.
- R1 (Filter Resistor) Opens: The signal path to the non-inverting input of U1A is broken. Node C drops to the op-amp's bias voltage (1.65V). No AC signal reaches the gain stage.
- Rf (Feedback Resistor) Opens: U1B loses negative feedback. The op-amp acts as a comparator, slamming the output to the 3.3V rail whenever the input crosses the 1.65V bias threshold, resulting in a square wave that will fry the ESP32 ADC pin if not current-limited.
Breadboard Testing and Verification Protocol
Do not test this circuit on live mains immediately. Use a function generator to simulate the CT output and verify the analog signal chain step-by-step.
- Power the AFE: Connect VCC to 3.3V and GND to the ESP32 ground. Probe the voltage divider bias network to confirm exactly 1.65V DC at the op-amp non-inverting inputs.
- Inject Signal: Feed the simulated 60Hz + 25kHz composite signal into Node A.
- Verify Node B (HPF_IN): Probe with an oscilloscope. You should see the composite signal shifted to a 1.65V DC offset.
- Verify Node C (HPF_OUT): Probe U1A output. The 60 Hz component should be attenuated by at least -40dB (virtually invisible on the scope), leaving only the 25 kHz noise riding on the 1.65V bias.
- Verify Node D (AMP_OUT): Probe U1B output. The 25 kHz signal should now be amplified to roughly 2.4Vpp, centered on 1.65V.
- Verify Node E (ENV_OUT): Probe the envelope detector output. You should see a smooth DC pulse peaking near 2.8V corresponding to the bursts of 25 kHz noise, with the 60Hz ripple completely eliminated.
Decision Tree: Selecting the ADC Sampling Strategy
The final hurdle in embedding an arc circuit interrupter is getting the analog data into the ESP32 efficiently. The ESP32's internal 12-bit SAR ADC is capable of high sample rates, but it is notoriously noisy and susceptible to aliasing if fed raw RF. Below is the decision matrix for selecting the sampling topology.
| Condition / Requirement | Strategy A: Raw High-Speed ADC | Strategy B: External I2C ADC | Strategy C: Hardware Envelope Detector |
|---|---|---|---|
| If you need raw waveform data for FFT | Use ESP32 I2S with external ADC (e.g., ADS1115 is too slow; requires ADS4142). | Reject. I2C latency kills HF sampling. | Reject. Envelope destroys phase/frequency data. |
| If you only need arc burst detection (magnitude) | Overkill. Burns CPU cycles and memory buffering 100ksps data. | Reject. 860 SPS max on ADS1115 misses 10kHz bursts entirely. | Optimal. Converts HF bursts to DC pulses readable at 1ksps. |
| If BOM cost and board space are constrained | Requires expensive high-speed ADC ICs and strict PCB layout. | Adds $3-$5 and I2C pull-ups. | Requires one 1N4148 diode, one 10nF cap, one 100kΩ resistor. Total cost: <$0.05. |
The Concrete Pick: Hardware Envelope Detector to GPIO34
For a functional embedded arc fault monitor, you do not need to perform real-time Fast Fourier Transforms (FFTs) on the raw 100 kHz waveform. You only need to detect the presence and magnitude of the high-frequency bursts that characterize an arc.
The definitive choice is Strategy C: Build a passive hardware envelope detector at Node E.
- Diode: 1N4148 (fast switching, low capacitance).
- Filter Cap: 10 nF (holds the peak voltage of the HF bursts).
- Bleed Resistor: 100 kΩ to GND (discharges the cap between bursts).
This creates an RC time constant ($\tau$) of 1 millisecond. This is fast enough to track the onset of an arc fault, but slow enough to bridge the 8.3 ms zero-crossing gaps of the 60 Hz mains cycle, outputting a clean, steady DC voltage proportional to the arc intensity. Route this directly to ESP32 GPIO34 (an input-only pin with no internal pull-up conflicts). Sample GPIO34 at a modest 1,000 samples per second using the ESP-IDF ADC oneshot driver. If the sampled voltage exceeds a calibrated threshold (e.g., 400 mV above the 1.65V bias baseline) for more than 3 consecutive half-cycles, trigger your interrupt logic.
By offloading the high-frequency signal processing to analog silicon, you free the ESP32 to handle MQTT telemetry, solid-state relay tripping, and NEC Article 210.12 compliance logging without dropping a single WiFi packet. Stick to the Sallen-Key filter and the hardware envelope detector; it is the most robust, cost-effective topology for embedded mains diagnostics.
