When designing front-end AC/DC converters for 24V or 48V battery charging, UPS systems, or ham radio transceivers, the power factor correction (PFC) stage dictates your system's efficiency, thermal footprint, and grid compliance. While passive PFC relies on bulky low-frequency inductors, an active power supply PFC stage uses high-frequency switching to force the input current waveform to track the input voltage waveform. This achieves a power factor (PF) >0.95 and stabilizes the intermediate DC bus, allowing downstream converters to operate optimally across a universal AC input range.
Why Active PFC Matters for Battery and Inverter Systems
For loads exceeding 150W, the debate between linear and switching architectures is definitively settled. A 300W linear power supply delivering 24V at 12.5A requires a massive 400VA 50/60Hz iron-core transformer. It will weigh over 15 lbs, operate at roughly 55% efficiency, and dump 240W of waste heat into your enclosure. Switching architectures solve the weight and efficiency problems, but without PFC, the rectifier's bulk capacitor draws narrow, high-amplitude current spikes at the peaks of the AC sine wave. This yields a dismal PF of 0.5 to 0.6 and generates severe harmonic distortion.
Under IEC 61000-3-2 Class D limits, equipment drawing between 75W and 600W with a special input current waveform must meet strict harmonic current limits per watt. Active PFC is practically mandatory to pass these certifications for commercial 300W+ battery chargers and inverters.
Input Range and Protection Requirements:
A properly designed active PFC stage accepts a universal input of 85VAC to 264VAC. Because the PFC boost converter regulates its output to a fixed DC bus voltage (typically 380V–400VDC), the downstream DC-DC converter sees a stable input regardless of whether the grid is sagging at 90VAC or surging at 260VAC. Protection must include input overcurrent (slow-blow fuse), inrush current limiting (NTC thermistor with relay bypass), and PFC output overvoltage protection (OVP) to prevent catastrophic bus overvoltage if the feedback loop breaks.
PFC Topology Comparison: Boost vs. Interleaved vs. Bridgeless
Selecting the right PFC topology requires balancing efficiency, thermal management, EMI filtering complexity, and BOM cost. Below is a data-dense comparison of the four dominant topologies used in modern power supply PFC active designs.
| Topology | Peak Efficiency (230VAC) | Thermal Profile | EMI / Noise | Relative BOM Cost | Ideal Application |
|---|---|---|---|---|---|
| CCM Boost (Standard) | 95.5% - 96.5% | Moderate (Diode reverse recovery losses) | Moderate (Hard switching edges) | $ (Lowest) | <400W UPS, 24V/48V Battery Chargers |
| Interleaved Boost | 96.5% - 97.5% | Low (Heat spread across 2 phases) | Low (Input ripple current cancellation) | $$ | 400W - 1kW Telecom, Solar Inverters |
| Bridgeless Dual-Boost | 97.0% - 98.0% | Very Low (Eliminates bridge rectifier drop) | High (Severe common-mode noise issues) | $$$ | >1kW High-end Inverters, Server PSUs |
| Totem-Pole (GaN/SiC) | 98.5% - 99.0% | Minimal (Soft-switching, no diode losses) | Moderate (Requires careful layout) | $$$$ | >2kW Datacenter, EV Chargers |
For a 300W 24V battery charging application, the Continuous Conduction Mode (CCM) Boost remains the undisputed king of cost-to-performance. While bridgeless and totem-pole topologies offer marginal efficiency gains, the EMI filtering required to tame their common-mode noise often erases the BOM cost savings and board space advantages at lower power levels. If you are scaling up to a 1kW 48V solar charge controller, however, the Interleaved Boost becomes necessary to keep inductor core sizes manageable and to cancel input ripple current, reducing the required X-capacitance on the AC line filter.
300W 24V Active PFC Design Example: Specs and Component Selection
Let's specify a concrete 300W CCM Boost PFC front-end paired with an LLC resonant DC-DC stage to deliver a tightly regulated 24V @ 12.5A output for LiFePO4 battery charging.
PFC Stage Specifications and Parts
- Controller: Texas Instruments UCC28180 (CCM PFC controller, operates at 100kHz).
- Boost Inductor: 250µH. Core material: Sendust or KoolMu (e.g., Magnetics 77083-A7) to handle the ~4A peak current without saturating, while minimizing core losses at 100kHz.
- Switch (MOSFET): Infineon IPP60R120P7 (600V CoolMOS, 120mΩ Rds(on)). Super-junction MOSFETs are mandatory here to keep gate charge (Qg) low and minimize switching losses.
- Boost Diode: 650V Silicon Carbide (SiC) Schottky (e.g., Wolfspeed C3D06060A). SiC eliminates reverse recovery charge (Qrr), which drastically reduces turn-on losses in the MOSFET and slashes EMI.
- Bulk Capacitor: 220µF, 450V electrolytic (e.g., Rubycon MXG series), rated for 105°C and 3000 hours.
Ripple and Noise Expectations
A fundamental reality of single-phase active PFC is that instantaneous AC input power drops to zero at every AC zero-crossing, while the DC output demands constant power. The bulk capacitor must absorb this 120Hz (or 100Hz) energy deficit. We can calculate the expected peak-to-peak ripple voltage on the 390V DC bus:
ΔV = P_out / (2 * π * f_line * C_bulk * V_bus)
ΔV = 300W / (2 * π * 120Hz * 220µF * 390V) ≈ 4.64V peak-to-peak
This 4.6V p-p 120Hz ripple is completely normal and expected. The downstream DC-DC stage (an LLC resonant converter using a controller like the UCC25640) must have sufficient Power Supply Rejection Ratio (PSRR) at 120Hz to prevent this low-frequency bus ripple from modulating the 24V output. With a well-compensated LLC stage, the 24V output ripple will be dominated by the high-frequency switching ripple (typically <50mV p-p with 2x 1000µF low-ESR polymer output capacitors), making it safe for sensitive battery management system (BMS) telemetry circuits.
Thermal Management, Derating, and Protection Circuits
Thermal Budget and Heatsink Sizing
At 300W output and an estimated 96% PFC stage efficiency, the PFC stage dissipates roughly 12.5W. The SiC diode and the CoolMOS FET will split the majority of this heat. Assuming the MOSFET dissipates 6W and has a junction-to-case thermal resistance (θ_JC) of 0.8°C/W, and the thermal pad (θ_CS) is 0.5°C/W, we can calculate the required heatsink thermal resistance (θ_SA) to keep the junction below 100°C in a 40°C ambient environment:
θ_SA = (T_j - T_ambient) / P_diss - θ_JC - θ_CS
θ_SA = (100 - 40) / 6 - 0.8 - 0.5 = 8.7°C/W
A standard extruded aluminum heatsink with a 6°C/W to 8°C/W profile, mounted with proper thermal compound, will easily handle this. Ensure the PCB layout keeps the high di/dt loop (Bulk Cap → MOSFET → Inductor → Diode → Bulk Cap) as tight as possible to minimize parasitic inductance, which causes voltage ringing and excess heat.
Derating Curve
For enclosed battery chargers or UPS systems, ambient temperature inside the chassis can easily exceed room temperature. Apply the following derating profile to ensure electrolytic capacitor longevity:
- 0°C to 45°C: 100% continuous load (300W).
- 45°C to 70°C: Linear derating from 100% to 50% load.
- Above 70°C: Shutdown via thermal switch on the main heatsink.
Inrush and Protection Circuitry
When the AC line is applied, the 220µF bulk capacitor looks like a dead short. Without limiting, inrush current can exceed 100A, tripping upstream breakers and welding relay contacts. Use an Ametherm MS35 10-0 NTC thermistor (10Ω cold resistance) in series with the AC line. To prevent the NTC from overheating during continuous operation, use a timing circuit (or a microcontroller GPIO) to trigger a 12V SPST relay that bypasses the NTC after 1.5 seconds. For fault protection, a 5A 250VAC slow-blow fuse provides catastrophic short-circuit protection, while the UCC28180's internal OVP comparator latches the controller off if the feedback divider detects a bus voltage exceeding 415V.
