The exclusive or symbol represents a digital logic gate that outputs a HIGH (logic 1) state only when its inputs differ. If both inputs are HIGH or both are LOW, the output drops to LOW. In practical electronics and schematic capture, you will encounter this symbol in two primary formats: the traditional curved "D" shape with a double-curved input line (MIL/ANSI), and the rectangular box containing an "=1" (IEC). Below is the definitive reference for identifying, interpreting, and testing XOR logic across different standards and environments.

The Complete Exclusive Or Symbol Reference Table

Use this table to quickly identify which standard or context a specific exclusive or symbol belongs to, and what it means for your circuit design.

Standard / Context Visual Description Symbol / Text Typical Use Case
IEC 60617 / IEEE 91 Rectangular box with "=1" inside [=1] European schematics, PLC ladder logic, Siemens TIA Portal
Traditional / MIL-STD-806 D-shape with curved back, straight front, extra input curve ⊕ (Curved) US schematics, TI/NXP datasheets, hobbyist PCB design
XNOR (Inverted XOR) Either of the above with a bubble (inversion circle) on output [=1] with ○ Parity checkers, equality comparators (e.g., 74LS266)
Mathematics Circled plus sign ⊕ Boolean algebra textbooks, cryptography, Galois field math
Programming (C, Python, etc.) Caret character ^ Bitwise XOR operations in firmware and embedded C code

Regional and Standard Variants Explained

The biggest point of confusion for makers and junior engineers is seeing two completely different shapes for the exact same logic function. This split comes down to regional and organizational standards.

The Traditional Shape (ANSI/IEEE Std 91 & MIL-STD-806):
This is the distinctive curved shape with a secondary arc on the input side. It is the dominant standard in the United States and is used almost exclusively by major silicon manufacturers like Texas Instruments and NXP in their datasheets. If you are looking at the datasheet for a TI 74LS86 Quad XOR IC, you will see this traditional symbol. It is also the default in US-centric EDA tools like Altium Designer and KiCad when using standard logic libraries.

The Rectangular Shape (IEC 60617):
The International Electrotechnical Commission (IEC) mandates rectangular boxes for all logic gates, using internal text to define the function. An OR gate is labeled "≥1" (one or more inputs HIGH), while the exclusive or symbol is labeled "=1" (exactly one input HIGH). You will see this almost exclusively in European industrial automation, PLC wiring diagrams, and software like Siemens TIA Portal or Beckhoff TwinCAT.

Workbench Tip: If you are designing a board for a US client or submitting a schematic to a US-based open-source hardware repo, stick to the traditional MIL/ANSI curved symbols. If you are wiring a factory control panel in the EU or programming a European PLC, use the IEC "=1" rectangles to avoid confusion during inspection.

Symbols and Rows People Get Wrong

When reading complex schematics or tracing multi-layer PCBs, misinterpreting the exclusive or symbol can lead to hours of debugging. Here are the most common traps:

  • Confusing OR (≥1) with XOR (=1): In IEC schematics, a single pixel difference or a smudge on a printed schematic can turn an "=1" into a "≥1". Remember that a standard OR gate outputs HIGH if both inputs are HIGH. An XOR gate outputs LOW if both inputs are HIGH. This distinction is fatal in adder circuits where XOR handles the sum bit and OR/AND handles the carry bit.
  • Missing the Inversion Bubble (XNOR): The XNOR gate (like the 74LS266) is functionally an XOR with a NOT gate on the output. On traditional symbols, this is a small circle on the output pin. On IEC symbols, it's a circle on the output edge or a "=0" / negation bar. Failing to spot this bubble will cause your truth table to be exactly inverted, which is a common reason why a freshly soldered parity checker fails on the bench.
  • The Parity Generator Trap: Engineers often cascade XOR gates to build parity generators (e.g., tying the output of one XOR into the input of the next). In these cascaded chains, the symbol is still XOR, but the system-level function is parity detection. Do not assume a single XOR symbol in a feedback loop is just doing simple arithmetic; it is likely checking for bit-flips or generating a checksum.

Safe Interpretation When Markings Are Faded

Suppose you are salvaging components from a dead piece of industrial equipment or a vintage synthesizer. You pull a 14-pin DIP IC, but the silkscreen is scraped off or faded by flux residue. You suspect it is a 74LS86 (TTL Quad XOR) or a CD4070 (CMOS Quad XOR), but it could also be a 74LS00 (NAND) or 74LS02 (NOR). How do you safely verify the exclusive or symbol's physical counterpart without guessing?

Bench Testing a Mystery 14-Pin DIP:

  1. Identify Power Pins: For almost all standard 14-pin logic ICs, Pin 14 is VCC and Pin 7 is GND. Apply 5V to Pin 14 and ground Pin 7. (If it's a 4000-series CMOS like the CD4070, you can use up to 15V, but 5V is safe for testing both TTL and CMOS).
  2. Isolate Gate 1: The inputs for the first gate are typically Pins 1 and 2, with the output on Pin 3.
  3. Apply Logic Levels: Use jumper wires to tie Pins 1 and 2 to either GND (Logic 0) or VCC (Logic 1).
  4. Measure the Output: Set your multimeter to DC Voltage and probe Pin 3.
    • If 0,0 yields ~0V; 0,1 yields ~5V; 1,0 yields ~5V; and 1,1 yields ~0V — you have an XOR gate.
    • If 1,1 yields ~5V, it is an OR gate.
    • If 0,0 yields ~5V and 1,1 yields ~0V, it is a NAND gate.
Warning: Never apply voltage to the input pins of an unpowered CMOS IC (like the CD4070 or SN74LVC86A). This can forward-bias the internal ESD protection diodes, causing latch-up and permanently destroying the silicon. Always ensure VCC and GND are connected before applying logic levels to the inputs.

Exclusive Or Symbol FAQ

What does the exclusive or symbol mean in a wiring diagram?

In high-voltage or relay-based wiring diagrams, the exclusive or symbol represents an interlock or a two-way switching equivalent. It means the circuit will only be energized if one, and only one, of the control conditions is met. For example, in a motor control circuit, an XOR logic block might dictate that the motor runs if either the manual pushbutton is pressed OR the auto-sensor is triggered, but it will intentionally shut down if both are triggered simultaneously to prevent a mechanical collision or safety hazard.

How do I type the exclusive or symbol on a keyboard?

If you are writing firmware in C, C++, or Python, the bitwise exclusive or symbol is the caret: ^ (Shift + 6 on standard US keyboards). For example, result = A ^ B;. If you are writing documentation or Boolean algebra and need the mathematical circled plus (⊕), you can type it in Windows by holding Alt and typing 8853 on the numeric keypad, or on Mac by using the Character Viewer (Ctrl+Cmd+Space) and searching for "circled plus".

Why does my schematic use a rectangle with "=1" instead of the curved XOR shape?

Your schematic is following the IEC 60617 standard, which is the norm in European engineering, industrial automation, and PLC programming. The IEC standard abandoned the distinctive curved shapes (like the D-shape for AND/OR) in favor of uniform rectangular boxes to make complex programmable logic arrays easier to draw and parse. The "=1" inside the box explicitly tells the reader that the output goes HIGH only when the sum of the HIGH inputs equals exactly one. For a deeper look at how these logic functions translate to physical silicon, review the XOR and XNOR gate breakdown on All About Circuits.