The Capacitive Potential Divider Topology Explained
A capacitive potential divider uses the reactance of series-connected capacitors to step down an alternating current (AC) voltage. Unlike a resistive divider, which burns real power as heat to drop voltage, a purely capacitive divider relies on reactive impedance, dissipating near-zero real power. This makes it the mandatory topology for high-voltage AC measurement probes, snubber networks, and low-power capacitive power supplies.
The standard topology consists of three distinct nodes:
- Node A (Input): The AC source connection ($V_{in}$).
- Node B (Tap/Midpoint): The junction between the two capacitors where the divided output ($V_{out}$) is measured.
- Node C (Reference): The common ground or return path.
Place the top capacitor ($C_{top}$) between Node A and Node B, and the bottom capacitor ($C_{bot}$) between Node B and Node C. Because capacitive reactance ($X_C = \frac{1}{2 \pi f C}$) is inversely proportional to capacitance, the voltage drops inversely as well. The smaller capacitor drops the lion's share of the voltage. The governing equation for the ideal output voltage is:
$$V_{out} = V_{in} \times \left( \frac{C_{top}}{C_{top} + C_{bot}} \right)$$
For a deeper mathematical derivation of AC reactive dividers, refer to the foundational AC theory modules at Learn About Electronics.
Why Capacitive Over Resistive?
| Criteria | Capacitive Divider | Resistive Divider |
|---|---|---|
| Real Power Dissipation | Near zero (only ESR losses) | High ($P = V^2/R$), requires wattage-rated resistors |
| High Voltage Handling | Excellent (limited by dielectric breakdown) | Poor (resistors suffer from voltage coefficient and arcing) |
| Frequency Response | Ratio is theoretically frequency-independent | Flat until parasitic shunt capacitance ruins high-freq response |
| DC Compatibility | Blocks DC entirely | Passes DC and AC equally |
Design Walkthrough: 1000V to 1V AC Measurement Probe
Let's design a high-voltage probe to step down a 1000V RMS, 60Hz AC line to a safe 1V RMS signal for an oscilloscope or isolated ADC. We need an attenuation ratio of 1000:1.
Using the formula $V_{out}/V_{in} = C_{top} / (C_{top} + C_{bot})$, a 1000:1 ratio requires $C_{bot}$ to be roughly 999 times larger than $C_{top}$. Let's select $C_{top} = 100\text{ pF}$ and $C_{bot} = 0.1\text{ \mu F}$ (100,000 pF).
Component Selection:
- $C_{top}$ (100 pF): Must withstand the full 1000V RMS (approx 1414V peak) plus a safety margin. We will use a Vishay HVCC series 100pF, 3kV radial ceramic capacitor. These are specifically engineered for high-voltage AC line applications with low dissipation factors.
- $C_{bot}$ (0.1 µF): Only sees ~1V RMS, so voltage rating is trivial. However, we need low equivalent series inductance (ESL) to maintain accuracy if harmonics are present. A WIMA MKS2 series 0.1µF, 63V metalized polyester film capacitor is ideal.
A purely capacitive divider will trap a dangerous DC charge if exposed to a transient or asymmetric fault. You must place a high-value bleed resistor (e.g., 1MΩ, 1/2W) in parallel with $C_{bot}$. This safely discharges Node B to Node C when power is removed and provides a DC return path for the input bias current of your measuring instrument.
Verification:
$V_{out} = 1000V \times \left( \frac{100\text{pF}}{100\text{pF} + 100,000\text{pF}} \right) = 1000V \times 0.000999 = 0.999V_{RMS}$. This is well within the 1% tolerance of standard measurement equipment. For more on practical high-voltage probe compensation, see Electronics Tutorials.
Element Behavior and Failure Mode Contrast
Understanding how the circuit reacts to component drift or catastrophic failure is critical when designing for mains-adjacent voltages. Below is the behavior matrix for the standard topology.
| Parameter Change | Effect on Node B ($V_{out}$) | Physical Reason |
|---|---|---|
| Increase $C_{top}$ | $V_{out}$ Increases | $X_{Ctop}$ drops, shifting more voltage across $C_{bot}$ |
| Increase $C_{bot}$ | $V_{out}$ Decreases | $X_{Cbot}$ drops, reducing its share of the voltage drop |
| Increase Frequency | $V_{out}$ Stays Constant (Ideal) | Both reactances scale equally; ratio is preserved |
| Add Resistive Load at Node B | $V_{out}$ Sags | Load parallels $C_{bot}$, lowering bottom-leg impedance and introducing phase shift |
The Extremes: Open and Short Failures
When designing protection circuitry (like TVS diodes or spark gaps at Node B), you must account for these failure extremes:
- $C_{top}$ Shorts: Node A connects directly to Node B. $V_{out}$ spikes to full $V_{in}$ (1000V). This is catastrophic for downstream silicon. Always place a clamping diode or gas discharge tube at Node B to shunt this fault to ground.
- $C_{top}$ Opens: The AC source is disconnected from Node B. Assuming a bleed resistor is present, $V_{out}$ safely drops to 0V.
- $C_{bot}$ Shorts: Node B is hard-shorted to Node C (Ground). $V_{out}$ forces to 0V. The full input voltage drops across $C_{top}$, which must be rated to survive this continuous stress without dielectric breakdown.
- $C_{bot}$ Opens: Node B loses its low-impedance ground reference. The input impedance of your oscilloscope (typically 1MΩ || 15pF) or stray PCB capacitance (2-5pF) becomes the new $C_{bot}$. Because this stray capacitance is tiny, $V_{out}$ will violently spike to near $V_{in}$, behaving exactly like a shorted $C_{top}$ scenario.
Step-by-Step Breadboard Testing Protocol
Never breadboard mains voltage. To validate your divider ratio and phase response safely, scale the design down using a benchtop function generator and an oscilloscope. For this test, we will use a 100:1 ratio with $C_{top} = 1\text{ nF}$ and $C_{bot} = 100\text{ nF}$.
- De-energize and Prep: Ensure the function generator (e.g., Rigol DG1022Z) output is disabled. Insert the 1nF and 100nF ceramic capacitors into the breadboard in series.
- Establish Nodes: Connect the function generator's BNC center conductor to Node A (top of 1nF). Connect the BNC ground clip to Node C (bottom of 100nF). Node B is the junction between the two caps.
- Probe Setup: Connect Oscilloscope Channel 1 to Node A (set to 1X or 10X, 2V/div). Connect Channel 2 to Node B (set to 1X, 50mV/div). Ensure both channels are set to AC Coupling to block any DC offset from the generator.
- Configure Source: Set the function generator to output a 10V peak-to-peak (Vpp) sine wave at 10 kHz.
- Power On and Measure: Enable the generator output. Trigger the scope on Channel 1. Measure the Vpp on Channel 2.
- Verify Ratio: Channel 2 should read approximately 100mV Vpp (a 100:1 attenuation). If the reading is erratic or significantly higher, check for breadboard stray capacitance or a damaged capacitor.
- Phase Check: Zoom in on the zero-crossings of both channels. In a purely capacitive divider with no resistive load, the zero-crossings should align perfectly (0° phase shift).
Frequently Asked Questions
Can a capacitive potential divider be used for DC?
No. At DC ($f = 0\text{ Hz}$), the capacitive reactance ($X_C$) approaches infinity. Capacitors block steady-state DC current entirely, meaning no continuous current flows through the series chain to establish a stable voltage division ratio. If you apply a DC step voltage, the capacitors will divide the voltage momentarily based on their capacitance ratio during the transient charging phase ($dV/dt$), but any leakage current or parallel load will quickly unbalance the node voltages until one capacitor hogs the entire DC supply voltage. For DC division, you must use a resistive topology.
How does frequency affect a capacitive voltage divider?
In an ideal mathematical model, the attenuation ratio of a capacitive divider is completely independent of frequency because both $X_{Ctop}$ and $X_{Cbot}$ scale inversely with frequency at the exact same rate. However, in real-world 2026 component design, parasitics ruin this perfection at high frequencies. Above a few hundred kilohertz, the Equivalent Series Inductance (ESL) of the capacitors and the stray capacitance of the PCB traces begin to dominate. The smaller capacitor ($C_{top}$) usually has a higher self-resonant frequency, meaning the divider ratio will drift unpredictably as you approach the VHF range. For high-frequency RF division, engineers use compensated RC dividers or coaxial attenuators instead.
What is the phase shift in a capacitive potential divider?
If the divider is unloaded (measured by an infinite-impedance ideal voltmeter), the phase shift between $V_{in}$ at Node A and $V_{out}$ at Node B is exactly 0°. While the current through the capacitors leads the voltage by 90°, the voltage drops across both capacitors are perfectly in phase with each other because they share the exact same series current. However, the moment you attach a real-world measuring device with a resistive input impedance (like a 1MΩ oscilloscope input) to Node B, you create a parallel RC network at the bottom leg. This introduces a phase lag, shifting $V_{out}$ slightly behind $V_{in}$. The heavier the resistive load relative to $X_{Cbot}$, the closer the phase shift approaches -90°.
