The fundamental formula for sizing decoupling capacitors on a calculator motherboard to prevent logic brownouts during ASIC switching is C = (I × Δt) / ΔV. When the main processor (like the custom 32-bit RISC in a Casio fx-991EX or the eZ80 in a TI-84 Plus CE) executes a heavy matrix inversion or triggers the LCD charge pump, it draws a transient current spike. The power delivery network (PDN) must supply this charge locally before the voltage droops below the silicon's brownout threshold. This guide breaks down the exact derivation, unit tracking, and real-world edge cases for calculator motherboard power integrity.
The Core Decoupling Formula for Calculator Motherboards
To maintain power integrity on a low-power digital board, the local decoupling capacitor must act as a transient energy reservoir. The baseline equation governing this charge-discharge event is derived from the fundamental capacitor current-voltage relationship (I = C × dV/dt), rearranged to solve for capacitance over a discrete time step.
Formula:
C = (I × Δt) / ΔV
| Symbol | Definition | Standard Unit | Typical Calculator Magnitude |
|---|---|---|---|
| C | Required decoupling capacitance | Farads (F) | 100 nF to 10 μF |
| I | Transient current spike drawn by the ASIC/LCD driver | Amperes (A) | 20 mA to 150 mA |
| Δt | Duration of the current spike (before VRM/battery responds) | Seconds (s) | 5 ns to 5 μs |
| ΔV | Maximum allowable voltage droop (Nominal VCC - Brownout VCC) | Volts (V) | 100 mV to 400 mV |
For a deeper look at how high-frequency bypassing interacts with PCB plane capacitance, refer to the Analog Devices practical decoupling guide, which details the anti-resonance peaks that occur when multiple capacitor values are placed in parallel on digital logic boards.
Assumptions, Unit Traps, and Realistic Magnitudes
When the Formula Applies (and Its Assumptions)
This formula applies strictly to high-frequency transient spikes (sub-microsecond to low-microsecond range) where the main battery or linear regulator cannot respond fast enough due to trace inductance. It assumes a constant current draw (I) during the transient window (Δt) and treats the capacitor as an ideal component. In reality, Equivalent Series Inductance (ESL) and Equivalent Series Resistance (ESR) will cause an immediate voltage step before the capacitive droop begins. For calculator motherboards operating at clock speeds under 50 MHz, the ideal capacitor assumption holds reasonably well for initial sizing, provided you select low-ESL Multilayer Ceramic Capacitors (MLCCs) in 0402 or 0603 packages.
Which Unit Mistakes Break the Calculation
The most common failure mode in PDN calculations is the micro-prefix trap. Engineers frequently plug in milliamps (10-3) and microseconds (10-6), but forget to convert the target capacitance from microfarads to base Farads.
Example of the trap: Calculating (45 × 15) / 150 and assuming the result is in microfarads, when the raw SI unit output is actually in Farads, leading to a capacitor selection that is one million times too small. Always convert all inputs to base SI units (Amperes, Seconds, Volts) before calculating, then convert the result to engineering prefixes (nF, μF).
Realistic Answer Magnitudes and DC Bias Derating
A realistic answer for a calculator motherboard CPU decoupling network is between 10 nF and 100 nF per power pin, supplemented by a bulk 4.7 μF to 10 μF capacitor near the battery input. However, you must account for DC bias derating. According to the Murata MLCC selection guide, a 10 μF X5R ceramic capacitor in a 0805 package may lose up to 60% of its nominal capacitance when biased at 3.3V. If your formula demands 4 μF, you must select a component rated for 10 μF or use a higher voltage rating (e.g., 6.3V or 10V) to mitigate the derating curve.
Rearranged Forms for PDN Debugging
When debugging a calculator motherboard that suffers from random resets or LCD ghosting, you rarely need to solve for C. Instead, you use the rearranged forms to identify the hidden variable causing the failure.
- Solving for Transient Current (I):
I = (C × ΔV) / Δt
Use case: You know the installed capacitance and the measured voltage droop on your oscilloscope; this tells you exactly how much current the ASIC is pulling during a clock edge. - Solving for Spike Duration (Δt):
Δt = (C × ΔV) / I
Use case: You know the ASIC's peak current draw from the datasheet and your bulk capacitor size; this tells you how many nanoseconds you have before the voltage rail collapses. - Solving for Voltage Droop (ΔV):
ΔV = (I × Δt) / C
Use case: You are evaluating an existing calculator motherboard layout to see if the current decoupling scheme will keep the 3.3V rail above the 2.9V brownout threshold during an LCD backlight inrush event.
Worked Problems: Sizing for LCD Driver and CPU Spikes
Problem 1: CPU Matrix Inversion Spike Sizing
Scenario: A custom scientific calculator motherboard operates at 3.3V. The ASIC brownout threshold is 3.1V. During a complex matrix inversion, the core draws a transient spike of 45 mA lasting for 15 nanoseconds. What is the minimum local decoupling capacitance required per power pin cluster?
Step 1: Identify and convert variables to base SI units.
- I = 45 mA = 45 × 10-3 A
- Δt = 15 ns = 15 × 10-9 s
- ΔV = 3.3V - 3.1V = 0.2V (200 × 10-3 V)
Step 2: Substitute into the formula with unit tracking.
C = (45 × 10-3 A × 15 × 10-9 s) / (200 × 10-3 V)
Step 3: Calculate the numerator (Charge, Q).
Q = 675 × 10-12 A·s (or Coulombs)
Step 4: Divide by the denominator (Voltage).
C = (675 × 10-12 C) / (0.2 V) = 3375 × 10-12 F
Step 5: Convert to standard engineering prefix.
C = 3.375 nF
Practical Selection: Select a standard 4.7 nF or 10 nF X7R MLCC in a 0402 package, placed within 2mm of the ASIC VCC pin to minimize trace inductance.
Problem 2: LCD Charge Pump Inrush Voltage Droop
Scenario: The LCD charge pump on a graphing calculator motherboard turns on, drawing 120 mA from the 3.3V rail for 5 microseconds. The board layout relies on a single 10 μF bulk MLCC near the battery connector. Will the voltage droop exceed the 250 mV safety margin?
Step 1: Identify and convert variables.
- I = 120 mA = 0.12 A
- Δt = 5 μs = 5 × 10-6 s
- C = 10 μF = 10 × 10-6 F (Assuming 0% DC bias derating for this baseline check)
Step 2: Use the rearranged formula for ΔV.
ΔV = (I × Δt) / C
Step 3: Substitute with unit tracking.
ΔV = (0.12 A × 5 × 10-6 s) / (10 × 10-6 F)
Step 4: Calculate.
ΔV = (0.6 × 10-6 C) / (10 × 10-6 F) = 0.06 V
Step 5: Convert to millivolts and evaluate.
ΔV = 60 mV
Conclusion: The 60 mV droop is well below the 250 mV safety margin. However, if the 10 μF capacitor is an X5R 0805 part biased at 3.3V, its effective capacitance might drop to 4 μF. Recalculating with C = 4 × 10-6 F yields ΔV = 150 mV, which is still safe but highlights why DC bias derating must be checked on calculator motherboards.
Frequently Asked Questions
Why does my calculator motherboard reset when the LCD backlight turns on?
This is a classic PDN failure caused by insufficient bulk capacitance or high trace inductance between the battery and the backlight driver. When the backlight LEDs engage, they pull a massive inrush current (often >100 mA). If the decoupling network cannot satisfy the C = (I × Δt) / ΔV requirement, the 3.3V rail sags below the microcontroller's brownout detection threshold (typically around 2.7V to 2.9V), triggering an automatic hardware reset. Adding a low-ESR 22 μF or 47 μF MLCC directly at the backlight driver's power input usually resolves this.
Can I use a single large electrolytic capacitor instead of multiple MLCCs on a calculator motherboard?
No. While a large aluminum electrolytic capacitor provides high bulk capacitance, its Equivalent Series Inductance (ESL) and Equivalent Series Resistance (ESR) are far too high to respond to the nanosecond-scale transient spikes generated by the calculator's digital logic. The high ESL effectively blocks high-frequency current delivery. You must use a distributed network of small, low-ESL MLCCs (like 100 nF 0402s) placed immediately adjacent to the ASIC power pins to handle high-frequency transients, supplemented by a larger MLCC for mid-frequency bulk storage.
How does trace inductance affect the decoupling formula for calculator motherboards?
The baseline formula assumes the capacitor is perfectly coupled to the load. In reality, PCB traces introduce inductance (roughly 1 nH per millimeter of trace length). This inductance creates an immediate voltage spike (ΔV = L × di/dt) the moment the current spike begins, before the capacitive droop even starts. If your traces are too long or too thin, the inductive kick alone can push the rail out of spec, rendering your calculated capacitance useless. To mitigate this, place decoupling capacitors on the same layer as the ASIC, use wide power pours, and utilize multiple vias to connect to internal ground planes, minimizing the total loop inductance.
