The XOR (Exclusive OR) logic gate outputs a HIGH (1) state only when its inputs are different. If you are reading a North American schematic, the ANSI/IEEE symbol is a D-shape with a curved back and a double-curved front. If you are reading a European or international schematic, the IEC symbol is a rectangular box with the qualifier '=1' or '⊕' inside. Regardless of the drawing standard, the physical silicon behavior remains identical: it is the fundamental building block for binary adders, parity checkers, and phase detectors.

The Complete XOR Symbol & Truth Table Reference

Before tracing wires or ordering silicon, you must be able to instantly recognize the gate on paper. Below is the definitive reference for the XOR logic gate symbol across the two dominant global drafting standards, alongside its mathematical behavior.

Attribute ANSI/IEEE Standard (US/Canada) IEC 60617 Standard (EU/Global)
Visual Shape D-shape with a curved back and double-curved front (resembles a shield) Standard rectangular box
Internal Qualifier None (shape alone defines the function) '=1' or '⊕' printed inside the box
Boolean Expression Y = A ⊕ B (or Y = A'B + AB')
Input A | Input B Output Y
0 | 0 0
0 | 1 1
1 | 0 1
1 | 1 0
Bench Tip: The easiest way to remember the XOR truth table is to think of it as an 'inequality detector' for digital signals. If A ≠ B, the output is HIGH. This is why XOR gates are heavily used in digital comparators and error-detection circuits.

Regional Standards: ANSI vs. IEC vs. Legacy

Understanding which standard applies to your region—and more importantly, to the legacy equipment you are servicing—prevents costly wiring errors.

ANSI/IEEE 91-1984 (North America)

The ANSI standard relies on distinct geometric shapes. The XOR gate features a curved back line that runs parallel to the double-curved front line. This is the critical visual distinction from a standard OR gate, which has a straight vertical back. If you see the double-curve on the input side and a secondary curve on the back, you are looking at an XOR gate. This standard dominates US-based aerospace, defense, and legacy industrial schematics.

IEC 60617 (International / European)

The IEC standard abandoned unique shapes in favor of uniform rectangular boxes with internal alphanumeric qualifiers. The XOR gate is denoted by '=1'. This literally translates to: 'The output is HIGH if exactly one input is HIGH.' While mathematically precise for 2-input gates, this symbol can cause confusion in multi-input scenarios (where XOR actually acts as an odd-parity generator, not a strict 'only one high' detector). Modern European PLC schematics and IEC-compliant CAD libraries (like EPLAN) use this exclusively.

Legacy MIL-STD and DIN

On older military or German DIN schematics, you may encounter a standard OR shape with a small '≠' (not equal) symbol next to it, or an IEC box with a '⊕' (circled plus) symbol. Treat these identically to the modern ANSI and IEC XOR symbols, respectively.

Rows and Symbols People Get Wrong

Misidentifying a logic gate on a faded schematic or a densely packed PCB silkscreen can lead to hours of debugging. Here are the most common points of failure when reading XOR symbols.

1. Confusing XOR with XNOR (The Missing Bubble)

The XNOR (Exclusive NOR) gate is simply an XOR gate with an inversion bubble on the output. On poorly printed schematics or degraded silkscreens, that tiny circle can disappear. The Fix: Trace the downstream logic. If the gate feeds into an active-low enable pin or is used in an equality comparator (outputting HIGH when inputs match), it is physically an XNOR, even if the bubble is faded.

2. Confusing XOR with OR (The Back Curve)

In the ANSI standard, the OR gate has a straight vertical line on the back (input side). The XOR gate has a curved line. When schematics are scaled down for PDF viewing, the gap between the back curve and the front curve of the XOR symbol can blur, making it look like a thick, straight line (an OR gate). The Fix: Zoom in to 200% and look for the distinct 'tail' or gap between the input line and the main body of the gate.

3. Safe Interpretation of Faded Markings

Warning: Never guess a logic function based on a partially visible symbol when working with mains-interfacing relays or high-current H-bridges. If the symbol is ambiguous, power down the board, use a multimeter in continuity mode to trace the IC pins to a known datasheet, or inject a 3.3V logic signal and observe the output with an oscilloscope.

From Symbol to Silicon: IC Selection Decision Path

Once you have identified the XOR logic gate symbol on your schematic, you need to select the physical integrated circuit. Do not just order a generic 'XOR chip'; the voltage domain and propagation delay will dictate your exact part number. Use this decision tree to terminate your component search.

If Your Application Requires... Then Select This Logic Family Exact Part Number (14-Pin DIP)
Standard 5V Logic (Breadboards, 5V Arduinos, general purpose) 74HC (High-speed CMOS, 2V to 6V range, ~15ns delay at 5V) SN74HC86N (Texas Instruments)
3.3V Microcontroller Interfacing (ESP32, Raspberry Pi, STM32) 74LVC (Low-voltage CMOS, 2.7V to 3.6V range, 5V tolerant inputs) SN74LVC86A (Texas Instruments)
Wide Voltage / Automotive / 12V Systems (Car electronics, 9V battery projects) CD4000 Series (3V to 15V range, slower ~60ns delay but massive voltage headroom) CD4030BE (Texas Instruments / ON Semi)
High-Speed RF / Clock Recovery (Phase detectors >50MHz) 74AC or ECL (Advanced CMOS or Emitter-Coupled Logic) 74AC86PC or MC100EP07 (XOR/XNOR)

Default Pick: If you are building a standard hobbyist project, educational kit, or 5V digital logic board, buy the SN74HC86N. It is the industry workhorse, costs under $0.50 in single quantities, and interfaces safely with almost all 5V logic families.

Real-World Pinouts and Wiring the 74HC86

The physical implementation of the XOR symbol usually comes in a quad-package (four independent 2-input XOR gates in one chip). Below is the standard 14-pin DIP pinout for the 74HC86 and CD4030. Note that while the logic is identical, the CD4000 series sometimes swaps the VCC and GND pins compared to the 74-series. Always verify the datasheet.

Standard 74HC86 Pinout (14-Pin PDIP)

  • Pin 1: 1A (Input 1, Gate 1)
  • Pin 2: 1B (Input 2, Gate 1)
  • Pin 3: 1Y (Output, Gate 1)
  • Pin 4: 2A (Input 1, Gate 2)
  • Pin 5: 2B (Input 2, Gate 2)
  • Pin 6: 2Y (Output, Gate 2)
  • Pin 7: GND (Ground)
  • Pin 8: 3Y (Output, Gate 3)
  • Pin 9: 3A (Input 1, Gate 3)
  • Pin 10: 3B (Input 2, Gate 3)
  • Pin 11: 4Y (Output, Gate 4)
  • Pin 12: 4A (Input 1, Gate 4)
  • Pin 13: 4B (Input 2, Gate 4)
  • Pin 14: VCC (Power, 2V to 6V)
Wiring Best Practice: Never leave unused XOR inputs floating. A floating CMOS input acts as an antenna, picking up EMI and causing the internal transistors to oscillate in their linear region. This will overheat the chip and cause excessive current draw. Always tie unused inputs directly to GND or VCC.

For deeper reading on logic family specifications and propagation delays, refer to the Texas Instruments Logic Guide. For foundational theory on how XOR gates construct half-adders and full-adders, All About Circuits provides excellent schematic breakdowns.