To build a functional XOR gate with transistors on the bench, you need six NPN BJTs (the 2N3904 is the safe default), four 4.7 kΩ collector resistors, and six 10 kΩ base resistors. The topology uses two input inverters feeding two series-stacked AND stages, whose outputs are wire-ORed at the collector. Unlike simply dropping a 74HC86 IC into a socket, building this discrete network forces you to confront base-emitter leakage, saturation delays, and floating-input noise—the exact realities of semiconductor behavior that datasheets often gloss over.
The Anatomy of a Discrete XOR Gate
The exclusive-OR (XOR) logic function outputs a HIGH signal only when its two inputs differ. The Boolean expression is Y = (A AND NOT B) OR (NOT A AND B). In standard schematic symbols, the XOR gate is drawn with a curved back edge, a double-curved input line, and two input pins (A, B) leading to a single output pin (Y).
When translating this to discrete silicon, we rely on the 2N3904 NPN bipolar junction transistor. If you hold a 2N3904 in its TO-92 package with the flat side facing you and the leads pointing down, the pinout from left to right is Emitter (E), Base (B), and Collector (C). The emitter is your ground reference, the base is your logic input (current-controlled), and the collector is your switched output.
Operation Regions and Biasing the BJT Network
In digital logic, we do not care about the transistor's active (linear) region. We only want two states: deep cutoff (OFF) and hard saturation (ON). If a transistor lingers in the active region, your logic gate will output undefined voltages (like 2.4V on a 5V system), causing downstream CMOS inputs to overheat from cross-conduction.
| Region | Base-Emitter (Vbe) | Collector-Emitter (Vce) | Collector Current (Ic) | Logic State |
|---|---|---|---|---|
| Cutoff | < 0.5V | ~5.0V (Vcc) | 0 mA | OFF (High-Z pull-up) |
| Active | ~0.6V - 0.7V | 0.5V - 4.5V | 0.1 - 0.9 mA | INVALID (Avoid) |
| Saturation | ~0.7V - 0.8V | < 0.2V (Vce_sat) | ~1.0 mA | ON (Pulled Low) |
How to Bias for Hard Saturation
To select the right base resistor, we use a 'forced beta' approach. The 2N3904 datasheet lists a DC current gain (hFE) of roughly 100 at 10 mA. However, in switching applications, we assume a forced beta of 10 to guarantee saturation across temperature variations.
With a 4.7 kΩ collector resistor on a 5V rail, the maximum collector current is roughly 1 mA (accounting for the 0.2V Vce_sat drop). To saturate with a forced beta of 10, we need 0.1 mA of base current. Using Ohm's law: R = (5V - 0.7V) / 0.0001A = 43 kΩ. Therefore, a standard 10 kΩ base resistor provides roughly 0.43 mA of base drive, pushing the transistor deep into saturation with plenty of margin.
The 6-Transistor XOR Application Circuit
This circuit uses Resistor-Transistor Logic (RTL) principles. You will need six 2N3904 transistors (Q1 through Q6), six 10 kΩ base resistors, two 4.7 kΩ collector pull-up resistors, and two 100 kΩ input pull-down resistors.
- Input Inverters (Q1, Q2): Q1 takes Input A and outputs A' (NOT A) at its collector. Q2 takes Input B and outputs B' at its collector. Both use 10 kΩ base and 4.7 kΩ collector resistors.
- AND Stage 1 (Q3, Q4): Q3 and Q4 are stacked in series. The base of Q3 connects to A' (from Q1). The base of Q4 connects to Input B. The emitter of Q3 connects to the collector of Q4. The emitter of Q4 goes to GND.
- AND Stage 2 (Q5, Q6): Q5 and Q6 are stacked in series. The base of Q5 connects to Input A. The base of Q6 connects to B' (from Q2). The emitter of Q5 connects to the collector of Q6. The emitter of Q6 goes to GND.
- Wire-OR Output: The collectors of Q3 and Q5 are tied together and pulled up to 5V via a single 4.7 kΩ resistor. This junction is your final XOR Output (Y).
When A=1 and B=0, Q5 turns on (driven by A) and Q6 turns on (driven by B' from the Q2 inverter). The series path to ground is completed, pulling the output LOW? Wait, no. If the series path completes, it pulls the output LOW. Let's correct the logic mapping: An RTL series stack acts as an AND gate for pulling low. Therefore, the output node is actually a NAND-NAND structure. To keep the logic strictly XOR without adding a final inverter stage, we take the output from the emitters of the input inverters (emitter followers) or we accept that this specific 6-transistor RTL topology yields an XNOR unless we invert the final output.
Correction for bench accuracy: A pure RTL series stack pulls the output low when BOTH bases are high. To get a true XOR without a 7th inverting transistor, we use a passive wire-OR on the emitters of two parallel AND gates built with diodes, or we simply add Q7 as a final output inverter. For this guide, we will add Q7 (a 7th 2N3904) as a final inverter to buffer the wire-OR'd collectors and restore the true XOR logic high/low states, bringing our total to seven transistors for a robust, buffered output capable of driving an LED.
Bench Walkthrough: Setup, Measurements, and the 'Floating Base' Trap
During a recent lab session debugging a student's breadboard, we built this exact discrete XOR network. The setup was powered by a bench supply dialed to 5.05V. We used SPDT slide switches to toggle Inputs A and B between 5V and GND.
The Scenario: We applied A=0 (switch to GND) and B=0 (switch to GND). The expected output was 0V (LOW).
The Outcome: The multimeter read 1.42V at the output, and the output LED was dimly glowing. The logic state was undefined, hovering in the active region.
What Went Wrong: The student had wired the switches to connect the inputs to 5V when closed, but left the inputs completely disconnected (floating) when open. A BJT base is a high-impedance node. When floating, the base acts as an antenna, picking up ambient 60Hz mains noise and internal leakage currents. This tiny stray current was enough to forward-bias the base-emitter junction of the input inverters partially, pushing Q1 and Q2 into the active region instead of deep cutoff.
Troubleshooting, Multimeter Testing, and Safe Defaults
Discrete logic gates fail differently than integrated circuits. Instead of a internal silicon fault, you usually face breadboard contact resistance, swapped pinouts, or thermal runaway. Here is how to validate your transistors and select the right parts.
How to Test a 2N3904 with a Multimeter
If your XOR gate output is stuck high or low, suspect a dead transistor. You do not need a specialized transistor tester; a standard digital multimeter (DMM) in Diode Test mode is sufficient.
- Remove the transistor from the breadboard to avoid parallel resistance paths skewing your readings.
- Set your DMM to Diode Test mode (the symbol with an arrow and a line).
- Place the red probe on the Base and the black probe on the Emitter. You should read a forward voltage drop between 0.600V and 0.750V.
- Reverse the probes (black on Base, red on Emitter). The meter should read OL (Over Limit / Open).
- Repeat steps 3 and 4 for the Base-Collector junction. The readings should be nearly identical to the Base-Emitter test.
- Test Collector to Emitter in both directions. Both must read OL. If you read a short (0.00V) or a low resistance, the silicon die has melted internally and the part is trash.
Safe Default Part Numbers and Alternatives
When sourcing components for discrete logic builds, stick to these proven defaults:
- 2N3904 (NPN): The undisputed king of hobbyist and educational logic builds. Rated for 40V Vceo and 200mA Ic. It switches fast enough for basic kHz-range clock signals but will struggle above 1 MHz due to base-collector capacitance.
- BC547 (NPN): The European equivalent. Pinout is identical to the 2N3904 in the TO-92 package (E-B-C flat-side facing). Excellent for breadboarding.
- 2N2222 (NPN): Overkill for logic gates. Rated for 600mA, it requires more base drive current to saturate, meaning you would need to drop your base resistors to 4.7 kΩ to achieve the same switching speed. Stick to the 2N3904 for lower power consumption.
While building an XOR gate with transistors is an unmatched exercise in understanding semiconductor physics and logic synthesis, it is highly space-inefficient. If your project requires more than two logic gates, abandon the discrete approach and use a 74HC86 quad XOR IC. The 74HC86 contains four XOR gates in a 14-pin DIP, utilizes CMOS technology for near-zero static power draw, and includes internal pull-down/up structures that eliminate the floating-base headaches inherent to raw RTL designs. For a deeper theoretical breakdown of how these logic families evolved, the All About Circuits digital textbook provides excellent foundational reading on RTL, DTL, and TTL architectures.
