The Exclusive-OR (XOR) gate outputs a logic HIGH only when its inputs differ. If you are reading a US-based schematic, the XOR circuit symbol is a D-shape with a curved back and a double-curve input line (ANSI/IEEE Std 91). If you are reading a European or international schematic, it is a rectangle containing =1 or ⊕ (IEC 60617). Below is the complete reference data to identify, wire, and debug these logic elements across global standards.
XOR Circuit Symbol & Standard Reference Table
The following table maps the visual representations of the XOR and XNOR gates to their governing standards. Use this to identify symbols on schematics, PCB silkscreens, and datasheets.
| Gate Type | ANSI/IEEE Std 91 (US) | IEC 60617 (Global/EU) | Boolean Expression | Truth Table Output |
|---|---|---|---|---|
| XOR (2-Input) | D-shape, curved back, double input curve | Rectangle with =1 or ⊕ |
Y = A ⊕ B | 0,1,1,0 |
| XNOR (2-Input) | XOR symbol + inversion bubble on output | Rectangle with =1 + inversion bubble |
Y = ~(A ⊕ B) | 1,0,0,1 |
| XOR (3-Input) | D-shape with 3 input lines | Rectangle with =1 (odd parity) |
Y = A ⊕ B ⊕ C | Odd parity checker |
| Programmable XOR | XOR symbol with control pin (EN/INV) | Rectangle with =1 and control input |
Y = A ⊕ (B·C) | Context dependent |
Note: The ANSI/IEEE standard relies on shape recognition (the "military" style), while the IEC standard relies on alphanumeric qualifiers inside a uniform rectangular boundary. Most modern EDA tools (KiCad, Altium) default to IEEE but allow IEC library swaps.
Rows People Get Wrong & Faded Marking Interpretation
When troubleshooting legacy hardware or reading poorly printed schematics, misidentifying an XOR gate can lead to hours of wasted bench time. Here are the most common points of confusion and how to resolve them.
The OR vs. XOR Curve Confusion
The most frequent mistake in ANSI/IEEE symbols is confusing a standard OR gate with an XOR gate. A standard OR gate has a single curved input line that meets the points of the D-shape. An XOR gate has a second, parallel curved line spaced slightly away from the main body. If the schematic is faded or the PCB silkscreen is scratched, assume it is a standard OR gate unless you can clearly trace the double-curve or verify the truth table with a logic probe.
The Missing Inversion Bubble (XOR vs XNOR)
A tiny inversion bubble on the output tail changes an XOR into an XNOR. On heavily reduced schematic PDFs or low-resolution fax prints, this bubble often disappears. Safe interpretation protocol: If the output behavior contradicts your XOR assumption (e.g., output is HIGH when both inputs are LOW), immediately suspect an XNOR. Verify by checking the IC part number (e.g., 74HC266 is XNOR, 74HC86 is XOR) rather than trusting the faded symbol.
Never use visual symbol identification alone when tracing logic on boards that interface with mains or high-voltage DC (e.g., solar inverter control boards). A misidentified XOR gate used in a zero-crossing detector can lead to catastrophic shoot-through in H-bridge MOSFETs. Always de-energize, lock out the power, and verify the logic function with a multimeter diode test or continuity check against the IC datasheet.
Real-World IC Pinouts & Logic Thresholds
Symbols on paper must eventually map to physical silicon. The two most common quad 2-input XOR ICs are the 74HC86 (CMOS, 2V-6V operation) and the CD4030 (4000-series CMOS, 3V-15V operation). Below is the standard 14-pin DIP pinout, which applies to both families.
| Pin | Function | Pin | Function |
|---|---|---|---|
| 1 | Input A1 | 8 | Output Y4 |
| 2 | Input B1 | 9 | Input B4 |
| 3 | Output Y1 | 10 | Input A4 |
| 4 | Input A2 | 11 | Output Y3 |
| 5 | Input B2 | 12 | Input B3 |
| 6 | Output Y2 | 13 | Input A3 |
| 7 | GND | 14 | VCC |
Voltage Thresholds: Why Your XOR is Outputting Garbage
A common bench failure occurs when mixing logic families. If you drive a 74HC86 (CMOS) with a 74LS (TTL) output at 5V, you may hit the threshold edge case. According to the Texas Instruments SN74HC86 datasheet, the minimum HIGH-level input voltage ($V_{IH}$) for 74HC at 4.5V VCC is 3.15V. However, a standard 74LS chip only guarantees a HIGH output ($V_{OH}$) of 2.7V. The 74HC86 will see 2.7V as an undefined state, resulting in oscillating or floating outputs. Fix: Use a 74HCT86 (TTL-compatible CMOS thresholds) or add a 1kΩ pull-up resistor to the LS output.
The Floating Input Hazard in CD4030
The 4000-series CD4030 is highly sensitive to floating inputs. Unlike bipolar TTL (which defaults HIGH when floating), CMOS inputs have near-infinite impedance. A floating pin on a CD4030 will act as an antenna, picking up 50/60Hz mains hum and causing the internal MOSFETs to rapidly switch, leading to excessive current draw and thermal destruction of the IC. Always tie unused XOR inputs to GND or VCC via a 10kΩ resistor.
FAQ: XOR Circuit Symbol & Logic Questions
What does the XOR circuit symbol mean in a parity checker?
In digital systems, the XOR circuit symbol represents an "odd parity" detector. When you cascade multiple XOR gates (e.g., chaining the output of Gate 1 into the input of Gate 2), the final output goes HIGH only if there is an odd number of HIGH inputs across the entire chain. This is heavily used in RAM error correction (ECC) and serial communication protocols like UART to generate and verify parity bits. For an even parity checker, the final XOR output is simply fed into an inverter (or an XNOR gate is used).
How do I draw an XOR circuit symbol in KiCad or Altium?
In KiCad, open the Symbol Library Editor and search for the 74HC86 or generic XOR symbol in the default 74xx or Logic libraries. KiCad defaults to the ANSI/IEEE D-shape. If your project requires IEC 60617 rectangular symbols (common in European industrial PLC schematics), you must download and enable the IEC logic library add-on, or manually draw a rectangle and place the text =1 inside using the text tool, ensuring the pin connections are mapped to the correct electrical nodes. In Altium, you can toggle between IEEE and IEC styles in the schematic preferences under Schematic > General > Symbol Standards.
Why does my XOR gate output high when both inputs are grounded?
If both inputs of an XOR gate are tied to GND (Logic 0), the output must be Logic 0. If you are measuring a HIGH output (or an oscillating voltage around 2.5V) with your multimeter, you are likely experiencing one of three issues: 1) Floating inputs: Your ground connection is broken or has high resistance, leaving the CMOS input floating. 2) Power rail bounce: The IC is experiencing severe ground bounce due to inadequate decoupling. Place a 100nF ceramic capacitor directly across pins 7 and 14. 3) Damaged IC: The output MOSFET is shorted to VCC due to a previous overvoltage event. Swap the IC and verify your input signals with an oscilloscope, as a multimeter's slow sampling rate will average out high-frequency oscillation into a false mid-rail DC reading.
Can I use an XOR gate as a phase detector?
Yes. When fed two square waves of the same frequency, an XOR gate acts as a simple digital phase detector. The duty cycle of the XOR output pulse is directly proportional to the phase difference between the two input signals. If the signals are perfectly in phase, the output is a constant LOW. If they are 180° out of phase, the output is a constant HIGH. This principle is the foundational building block of simple Phase-Locked Loops (PLLs) like the CD4046B, where the XOR output is filtered by an RC low-pass network to generate a DC control voltage for a VCO.
