The XNOR (Exclusive-NOR) logic gate outputs a HIGH (1) signal only when both inputs are at the exact same logic level. If the inputs differ, the output is LOW (0). It is the logical complement of the XOR gate and is fundamentally used as an equality detector in digital comparators, parity checkers, and phase-locked loops.
Below is the definitive reference for the XNOR logic gate truth table, moving from the pure boolean standard to the real-world silicon specifications you need to actually wire one on a breadboard or PCB.
The Boolean XNOR Logic Gate Truth Table (IEEE 91a Standard)
The following table defines the ideal logical behavior of a 2-input XNOR gate, standardized under IEEE Std 91a-1991 (Standard Graphic Symbols for Logic Functions).
| Input A | Input B | Output Q (XNOR) | Common Use Case |
|---|---|---|---|
| 0 | 0 | 1 | Both lines idle/LOW (Match detected) |
| 0 | 1 | 0 | Signal mismatch (Error/Parity fail) |
| 1 | 0 | 0 | Signal mismatch (Error/Parity fail) |
| 1 | 1 | 1 | Both lines active/HIGH (Match detected) |
Bookmark Quick-Jump: If you are debugging a parity circuit and your inputs are mismatched (0,1 or 1,0), your XNOR output will definitively pull LOW. If you are building a digital comparator, a HIGH output confirms A = B.
The Engineering Truth Table: Voltage Thresholds & Logic Families
A boolean table assumes perfect 0V and 5V signals. In reality, silicon requires specific voltage thresholds to register a HIGH or LOW. Which column applies to your installation depends entirely on the logic family you select. Mixing families without checking these thresholds is the #1 cause of 'ghost' logic errors on the bench.
The table below compares the three most common XNOR ICs: the modern CMOS SN74HC266, the legacy TTL SN74LS266, and the wide-voltage CD4077B.
| Parameter | SN74HC266 (CMOS) | SN74LS266 (TTL) | CD4077B (4000-Series) |
|---|---|---|---|
| Operating VCC Range | 2.0V to 6.0V | 4.75V to 5.25V | 3.0V to 18.0V |
| V_IH (Min HIGH Input) | 3.15V (at VCC=4.5V) | 2.0V | 3.5V (at VCC=5V) / 11V (at VCC=15V) |
| V_IL (Max LOW Input) | 1.35V (at VCC=4.5V) | 0.8V | 1.5V (at VCC=5V) / 4V (at VCC=15V) |
| Output Type | Open-Drain | Open-Collector | Push-Pull |
| Max I_OL (Sink Current) | 6 mA | 16 mA | 6.8 mA (at VCC=15V) |
Derating Propagation Delay: How Loading Modifies the Base Value
Datasheets list a base propagation delay ($t_{pd}$), but this value is only valid for a specific capacitive load ($C_L$). How do derating rows modify the base value? Every picofarad (pF) of parasitic capacitance added by your PCB traces, breadboard contacts, or downstream gate inputs acts as a tiny capacitor that the IC must charge before the voltage crosses the threshold.
For the SN74HC266 operating at 5V:
- Base Value: $t_{pd}$ is typically 18 ns at $C_L$ = 15 pF.
- Derating Factor: Add approximately 0.4 ns for every 1 pF of additional load.
- Real-World Example: If you are driving a long wire or multiple inputs totaling 50 pF of capacitance, your delay increases by 35 pF over the baseline. Calculation: 18 ns + (35 pF × 0.4 ns/pF) = 32 ns total propagation delay.
If you are designing a high-speed clock tree or an RF phase detector, a 32 ns skew will destroy your timing margins. In those cases, you must buffer the XNOR output with a dedicated high-speed driver or minimize trace lengths to keep $C_L$ under 20 pF.
XNOR IC Decision Tree: Picking Your Exact Part Number
Stop guessing which chip to drop into your cart. Follow this decision path to terminate on the exact part number for your build.
| Your Project Constraint | If Yes... | If No... |
|---|---|---|
| Are you running off a battery or unregulated supply that swings between 3V and 15V? | Move to wide-voltage CMOS. | Move to 5V-regulated logic. |
| Do you need to wire-OR multiple XNOR outputs together on a single bus? | You require Open-Drain outputs. | You require Push-Pull outputs. |
| Are you interfacing directly with legacy 5V TTL microcontrollers (like older PICs or 8051s)? | You need TTL-compatible input thresholds (V_IH = 2.0V). | Standard CMOS thresholds are fine. |
Final Part Number Recommendations
- Default Pick (5V Breadboard Prototyping): Buy the CD4077BE. It operates at 5V, features standard push-pull outputs (no pull-up resistors needed), and is highly forgiving with slow-rising signals. (Use this if you just want it to work without extra passives).
- Bus/Wire-OR Pick (5V Strict): Buy the SN74HC266N. Use this when you are building a shared interrupt line or parity bus where multiple XNOR gates must pull a single line LOW without fighting each other. Remember your 4.7kΩ pull-ups.
- High-Voltage / Automotive Pick: Buy the CD4077BE and run it at 12V. It handles up to 18V, making it ideal for 12V automotive or solar logic monitoring where 5V regulators are undesirable.
What the Truth Table Cannot Tell You (Edge Cases)
The boolean truth table assumes digital perfection. Here is what it hides, and what will cause your circuit to fail if you ignore it:
- Floating Inputs Cause Massive Current Draw: In CMOS families (HC and CD4000), an unconnected input pin does not default to LOW. It floats into the analog transition region between $V_{IL}$ and $V_{IH}$. This turns on both the PMOS and NMOS transistors inside the gate simultaneously, creating a direct short from VCC to GND. The IC will overheat, and your battery will drain in hours. Fix: Always tie unused XNOR inputs to GND or VCC with a 10kΩ resistor.
- Metastability on Simultaneous Transitions: If Input A and Input B change states at the exact same picosecond (e.g., both transitioning from 0,1 to 1,0), the internal flip-flops or transistor pairs can enter a metastable state. The output may oscillate at high frequencies or hang at an intermediate voltage (e.g., 2.5V) for several nanoseconds before resolving. Fix: Never use an XNOR gate directly as a clock source; always pass the output through a synchronizing flip-flop if feeding a microcontroller interrupt.
- Slow Rise Times Destroy the Output: The truth table assumes instantaneous transitions. If your input signal is a slow analog ramp (like a charging capacitor), the XNOR gate will rapidly toggle its output as it crosses the threshold multiple times due to noise. Fix: Feed slow signals through a Schmitt-trigger buffer (like the 74HC14) before they hit the XNOR inputs.
By treating the XNOR logic gate truth table not just as a boolean concept, but as a physical silicon component with voltage thresholds, capacitive derating, and output-stage limitations, you eliminate 90% of the debugging headaches common in digital logic design.
