The symbol for an XNOR gate (Exclusive-NOR) represents a digital logic gate that outputs a HIGH (1) only when both inputs are at the same logic level. On schematics, you will encounter two primary visual standards: the ANSI/IEEE 'military' shape (a curved XOR shape with an inversion bubble on the output) and the IEC 60617 rectangular shape (a rectangle with an '=' or 'XNOR' designator and an inversion bubble). Knowing which standard applies to your region—and how to identify the physical ICs behind them—is critical for accurate bench troubleshooting and PCB design.
| Standard | Visual Description | Logic Equation | Truth Table (A,B → Y) | Regional Dominance |
|---|---|---|---|---|
| ANSI/IEEE Std 91 | Curved D-shape with convex back, output bubble | Y = A ⊙ B | 0,0→1 | 0,1→0 | 1,0→0 | 1,1→1 | US, Military, Legacy Aerospace |
| IEC 60617 | Rectangle with '=' inside, output bubble | Y = (A ⊕ B)' | 0,0→1 | 0,1→0 | 1,0→0 | 1,1→1 | EU, UK, Modern Global Auto/Industrial |
| DIN 40700 (Obsolete) | Rectangle with '≥1' and output bubble | Y = A ⊙ B | 0,0→1 | 0,1→0 | 1,0→0 | 1,1→1 | Older German/European schematics |
| NEMA / Electrical | Ladder logic: Parallel NO/NC contacts in series | Y = (A'B')+(AB) | 0,0→1 | 0,1→0 | 1,0→0 | 1,1→1 | US Industrial PLC Ladder Diagrams |
Decoding the Standards: ANSI/IEEE vs. IEC 60617
When reading a schematic, the standard used usually tells you where and when the design originated. The IEC 60617 standard has largely taken over modern international and European designs, favoring rectangular boxes for all logic functions to make complex VLSI (Very Large Scale Integration) schematics easier to draw and parse. In the IEC system, the XNOR is denoted by an equality sign (=) inside the rectangle, indicating the output is high when inputs are equal, paired with a negation circle (bubble) on the output pin.
Conversely, the ANSI/IEEE Std 91-1984 distinct-shape symbols remain the default in US universities, military documentation, and legacy American aerospace schematics. The XNOR is drawn as an XOR gate (which has a curved back and an extra curved line spaced slightly away from the input side) with an inversion bubble on the output nose.
In both ANSI and IEC standards, the inversion bubble is the only visual difference between an XOR and an XNOR gate. On heavily reduced photocopies, low-resolution PDFs, or poorly printed silkscreens, this bubble can easily vanish. Always verify the logic function with a multimeter or logic probe rather than trusting a potentially degraded visual symbol.
Common XNOR ICs: Pinouts and Practical Bench Notes
If you are prototyping on a breadboard or repairing a logic board, you will rarely see a discrete XNOR gate built from transistors. You will use standard 14-pin DIP or SOIC ICs. The most common families are the 74-series (TTL/CMOS) and the 4000-series (CMOS). Below is a data-dense reference for the exact part numbers you will encounter at the bench.
| Part Number | Logic Family | Gates per IC | Output Type | VCC Range | Typical Prop. Delay |
|---|---|---|---|---|---|
| SN74HC266 | High-Speed CMOS | Quad 2-Input | Open-Drain | 2.0V to 6.0V | ~14 ns @ 5V |
| SN74LS266 | Low-Power Schottky TTL | Quad 2-Input | Open-Collector | 4.75V to 5.25V | ~22 ns @ 5V |
| CD4077 / HEF4077 | Standard CMOS | Quad 2-Input | Push-Pull | 3.0V to 15.0V | ~60 ns @ 5V |
| 74LVC2G266 | Low-Voltage CMOS | Dual 2-Input | Push-Pull | 1.65V to 5.5V | ~4.5 ns @ 3.3V |
The Open-Drain Gotcha: Notice that the ubiquitous 74x266 chips (both HC and LS variants) feature open-drain or open-collector outputs. This is a massive trap for beginners. Unlike the CD4077 which has a standard push-pull output that can source and sink current directly, an open-drain XNOR gate can only pull the output line to GND (LOW). It cannot drive the line HIGH. If you connect an LED directly from the output of a 74HC266 to VCC, it will work when the output is LOW, but if you connect it to GND expecting it to light up on a HIGH output, it will remain dead. You must use a pull-up resistor (typically 4.7kΩ to 10kΩ) on the output pin to achieve a HIGH logic level.
Why do manufacturers use open-drain for XNOR/XOR gates? It allows designers to wire-OR multiple gate outputs together on a single bus without causing a short circuit if one gate outputs HIGH while another outputs LOW. For a complete electrical breakdown of this behavior, refer to the Texas Instruments SN74HC266 Datasheet.
Rows People Get Wrong and Faded Marking Recovery
When working with physical hardware or deciphering old schematics, misinterpreting the symbol for an XNOR gate leads to hours of wasted debugging. Here are the most common errors and how to resolve them.
The 'Rows People Get Wrong' Notes
- IEC '=' vs. Buffer: In IEC 60617, a simple buffer (non-inverting) is a rectangle with a '1' inside. An XNOR is a rectangle with '=' inside plus an output bubble. If you miss the bubble, you will assume the gate is a non-inverting equality checker (which doesn't exist as a standard single gate) or misread it as a standard buffer.
- Active-Low Inputs: Sometimes an XNOR gate is drawn with bubbles on the inputs rather than the output. By De Morgan's Laws, an XNOR gate with inverted inputs is logically identical to an XOR gate. Schematic designers do this to match the active-low logic of the preceding stage, but it frequently confuses hobbyists who think the IC itself has changed.
- 3-Input XNOR Confusion: Standard XNOR gates are 2-input. If you see a 3-input symbol, it is usually an XOR gate with an inverter, or it represents a parity checker. True 3-input XNOR ICs (like the 4000-series equivalents) are exceedingly rare; designers typically cascade two 2-input XNOR gates instead.
Safe Interpretation When Markings are Faded or Missing
If you are reverse-engineering a PCB where the silkscreen has flaked off, or an IC's laser-etched part number is scratched beyond recognition, do not guess the logic function based on trace routing alone. Use your multimeter to map the physical pins.
- Identify VCC and GND: Set your multimeter to continuity mode. Probe the pins against known ground planes (like the shield of a USB port or a large ground via). Pin 7 is almost always GND and Pin 14 is VCC on 14-pin DIP logic ICs, but verify this first.
- Map the Diode Junctions: Switch your multimeter to the Diode Test setting. Place the red probe on the GND pin and touch the black probe to the other pins. You are measuring the internal ESD protection diodes. Input pins will typically show a forward voltage drop of 0.5V to 0.7V. Output pins may read differently or show 'OL' (Open Loop) depending on the internal transistor topology.
- Trace the Logic: Once you identify the input and output pins for a single gate block, power the board (if safe) and use a logic probe. Force the inputs HIGH and LOW using a jumper wire and a 1kΩ resistor. If the output goes HIGH only when both inputs match (0,0 or 1,1), you have definitively identified an XNOR gate, regardless of what the faded schematic symbol claims.
For deeper verification on CMOS families like the NXP HEF4077B, remember that unconnected (floating) CMOS inputs can drift into the linear region, causing the IC to draw massive quiescent current and overheat. Always tie unused XNOR gate inputs to VCC or GND via a resistor during bench testing to prevent thermal destruction of the chip.
