The XNOR (Exclusive-NOR) gate symbol represents a digital logic gate that outputs a HIGH (1) only when both inputs are at the exact same logic level (both 0 or both 1). In schematic form, you will encounter two primary visual standards: the ANSI/IEEE curved D-shape with an inversion bubble, and the IEC rectangular box marked with "=1" and an inversion bubble. Below is the complete reference matrix for identifying, interpreting, and sourcing XNOR logic across global standards.
XNOR Gate Symbol & Logic Reference Matrix
| Standard / Variant | Visual Symbol Description | Boolean Expression | Practical Meaning & Behavior | Common IC Part Numbers |
|---|---|---|---|---|
| ANSI/IEEE Std 91 (Standard) | D-shaped body with a curved back, single output line terminating in a small circle (bubble). | Y = A ⊙ B or Y = (A⊕B)' |
Outputs HIGH when inputs match. The bubble denotes logical inversion of an XOR gate. | 74HC266, 74LS266, CD4077 |
| IEC 60617 (Standard) | Rectangular box. Inside left: "=1". Right edge: output line with a small circle (bubble). | Y = A ⊙ B | "=1" means output is active when exactly one input is HIGH (XOR); the bubble inverts this to XNOR (active when inputs are equal). | HEF4077B, SN74HC266 |
| ANSI Open-Collector / Open-Drain | Standard ANSI D-shape, but the output line features a small diamond symbol before the inversion bubble. | Y = A ⊙ B (Open-Drain) | Output transistor only pulls LOW. Requires an external pull-up resistor to achieve a HIGH state. Common in bus-wired logic. | 74LS266 (TTL), 74HC266 (CMOS) |
| IEC with Active-Low Inputs | Rectangular box with "=1" inside. Input lines on the left have bubbles; output line on the right has a bubble. | Y = A' ⊙ B' | Functionally identical to standard XNOR, but drawn to emphasize that the preceding circuitry is asserting LOW signals to trigger the gate. | Custom ASICs, FPGA schematic captures |
Regional Standards: ANSI/IEEE vs. IEC 60617
Which standard applies to your schematic depends heavily on your region, the age of the design, and the EDA software defaults.
ANSI/IEEE Std 91-1984 (Mil-Spec / US Legacy): This is the familiar "shape-based" symbology. It uses distinct geometric shapes to represent logic functions (AND is flat-backed, OR is curved-backed). The XNOR gate is drawn as an XOR gate (D-shape with a detached curved back line) with an inversion bubble on the output. If you are reading older US military schematics, repairing vintage test equipment, or using default libraries in older versions of OrCAD, you will see this standard. It is highly intuitive for visual tracing because the shape itself tells you the gate type.
IEC 60617 (European / Modern Industrial): The International Electrotechnical Commission standard abandons unique shapes in favor of standardized rectangular boxes. Logic functions are denoted by internal qualifiers. For an XNOR gate, the qualifier is =1 combined with an output negation bubble. The =1 technically defines an XOR function (output is 1 if exactly one input is 1), and the bubble inverts it. If you are designing for modern European industrial PLCs, using Altium Designer's IEC libraries, or reading contemporary automotive wiring diagrams, this is the standard you must interpret.
Notice the third row in the table above. The most common through-hole XNOR ICs (like the TI SN74HC266 and the legacy 74LS266) feature open-collector or open-drain outputs. They do not have internal push-pull transistors to drive the line HIGH. If you wire a 74HC266 directly to an LED or a microcontroller input without a pull-up resistor (typically 4.7kΩ to 10kΩ to VCC), the output will float when it should be HIGH, resulting in erratic logic levels and phantom triggering. If you need a true push-pull XNOR output without external resistors, use the 4000-series CMOS CD4077 instead.
Rows and Symbols People Get Wrong
When reading complex schematics, a few specific symbol variations consistently cause miswiring and debugging headaches on the bench.
1. Confusing the IEC "=1" Bubble with an OR Gate
In IEC 60617, an OR gate is represented by a rectangle with the qualifier ≥1 (meaning output is HIGH if one or more inputs are HIGH). An XOR gate is =1 (output HIGH if exactly one input is HIGH). An XNOR is =1 with an output bubble. Hobbyists frequently misread the =1 as a standard OR gate, wire the circuit, and spend hours wondering why the logic fails when both inputs are HIGH (an OR gate would output 1; an XNOR outputs 0).
2. Missing the Open-Collector Diamond
In ANSI schematics, the open-collector/open-drain indicator is a tiny diamond placed on the output pin, right before the inversion bubble. On printed schematics or low-resolution PDFs, this diamond often looks like a smudge or is mistaken for a standard junction dot. If you assume it is a standard push-pull output and omit the pull-up resistor, the circuit will fail. Always zoom in on the output node of 74LS/74HC XNOR gates in legacy schematics.
3. Active-Low Input Bubbles vs. Inversion
Sometimes an XNOR gate is drawn with bubbles on the inputs rather than the output. Mathematically, (NOT A) XNOR (NOT B) yields the exact same truth table as A XNOR B. Drafters do this to maintain "bubble-to-bubble" logic flow (active-low output from a previous stage feeding an active-low input). The gate is still an XNOR, but the physical IC pin expects a LOW voltage to register as a logical "1" for that specific internal node.
Identifying XNOR Gates with Faded or Missing Markings
When repairing damaged PCBs, salvaging components, or reverse-engineering a board where the silkscreen has been burned off or sanded away, you cannot rely on the printed XNOR symbol or IC part number. Here is the systematic bench procedure to identify an unknown XNOR gate IC.
Step 1: Locate VCC and GND
For standard 14-pin DIP logic ICs, Pin 7 is almost universally Ground (GND) and Pin 14 is VCC. Use your multimeter in continuity mode to trace Pin 7 to the ground plane, and Pin 14 to the power decoupling capacitor. If the IC is a 4000-series CMOS (like the CD4077), it can operate from 3V to 15V. If it is 74HC, it is strictly 2V to 6V.
Step 2: The Protection Diode Test
Switch your multimeter to Diode Test mode. Place the red probe on VCC (Pin 14) and the black probe on the suspected input pins (typically 1, 2, 5, 6, 8, 9, 12, 13 for a quad-gate IC). You should read a forward voltage drop of approximately 0.5V to 0.7V, indicating the internal ESD protection diodes. Output pins (3, 4, 10, 11) will often read differently or open-loop depending on the internal transistor topology.
Step 3: Live Logic Verification
If the chip is unmarked and you suspect it is an XNOR, power the board using a current-limited bench supply set to 5.0V with a 50mA current limit to prevent catastrophic shorts. Apply 5V (logic 1) and 0V (logic 0) to the input pairs using 1kΩ current-limiting resistors.
- Apply 0V / 0V → Measure output. If HIGH (~5V), proceed.
- Apply 5V / 5V → Measure output. If HIGH (~5V), proceed.
- Apply 0V / 5V → Measure output. If LOW (~0V), proceed.
- Apply 5V / 0V → Measure output. If LOW (~0V), you have confirmed an XNOR truth table.
Note: If the output floats (reads ~2.5V or drifts) during the HIGH states in Step 3, you have successfully identified an open-drain XNOR gate (like the 74HC266). Solder a 10kΩ pull-up resistor from the output pin to VCC and re-test to confirm the HIGH state snaps to 5V.
