What Is a Tri-State Buffer? Circuit Theory and Part Selection

A tri-state buffer is a digital logic gate that outputs a HIGH, a LOW, or a high-impedance (Hi-Z) state, effectively disconnecting its output from the circuit when disabled. In a real circuit, this changes everything about how you route signals: it allows multiple active devices to share a single physical wire (a bus) without shorting each other out. If you have ever wondered how a microcontroller talks to three different SPI sensors on the same MISO line, or how memory chips share data pins without fighting, the tri-state buffer is the answer.

The Core Mechanism: HIGH, LOW, and the Magic of Hi-Z

A standard non-inverting buffer has two states: it drives the output pin to VCC (HIGH) or GND (LOW). It does this using a totem-pole arrangement of two transistors—a PMOS pulling up to VCC and an NMOS pulling down to GND. When the input is HIGH, the PMOS turns on; when LOW, the NMOS turns on.

A tri-state buffer adds a third control pin, usually labeled Output Enable (OE) or Output Control (OC). This pin acts as a master kill switch for both internal transistors simultaneously.

When in the Hi-Z state, the pin does not output 0V. It outputs nothing. The leakage current in Hi-Z is typically less than 1 µA, presenting an impedance greater than 100 MΩ to the rest of the circuit. To the rest of the bus, the disabled buffer simply does not exist.

The Numeric Reality: Why Bus Contention Fries Chips

To understand why tri-state buffers are mandatory for shared buses, we need to look at the math behind bus contention. Bus contention occurs when two standard push-pull outputs are tied to the same wire, and one tries to drive HIGH while the other tries to drive LOW.

Let us run a worked numeric example using a standard 74HC series CMOS logic chip operating at 5V. The on-resistance ($R_{DS(on)}$) of the internal output transistors is typically around 25Ω. If Chip A drives HIGH (5V) and Chip B drives LOW (0V) on the same wire, you have created a direct short circuit through the silicon.

• Total Resistance: 25Ω (Chip A PMOS) + 25Ω (Chip B NMOS) = 50Ω
• Short Circuit Current: $I = V / R = 5V / 50Ω = 100mA$
• Power Dissipation: $P = V imes I = 5V imes 0.1A = 500mW$

The absolute maximum continuous current for a standard 74HC pin is 25mA. A 100mA spike is four times the safe limit. Furthermore, dissipating 500mW inside a tiny SOT-23 or SOIC package (which has a thermal resistance of roughly 200°C/W) causes an immediate 100°C temperature spike. The silicon will overheat, potentially causing catastrophic thermal failure, melting the bond wires, or triggering a destructive latch-up condition.

A tri-state buffer prevents this. By putting Chip B into Hi-Z, its internal resistance becomes >100 MΩ. The current drops to virtually zero, and both chips survive.

Where You Meet Tri-State Buffers in Practice

You will rarely see a standalone tri-state buffer in a simple LED-blinking circuit. They are infrastructure components used in specific topologies:

1. SPI MISO Lines:
The Serial Peripheral Interface (SPI) uses a shared Master-In-Slave-Out (MISO) line. If you have an SD card, an IMU, and a DAC all sharing one ESP32 MISO pin, only one device can drive that line at a time. When a device's Chip Select (CS) pin is HIGH (unselected), its internal MISO buffer must go Hi-Z. If a sensor module lacks this internal tri-state logic, you must add an external tri-state buffer to its MISO line before connecting it to the bus.

2. Parallel Memory Buses:
Chips like the Microchip 23LC1024 1-Mbit SRAM use 8 bidirectional data pins. When the microcontroller is writing to the RAM, the RAM's output buffers go Hi-Z so the microcontroller can drive the pins. When reading, the microcontroller's pins go Hi-Z (or are configured as inputs) and the RAM drives the bus.

3. Multiplexing Analog/Digital Signals:
If you need to route one of four different sensor signals into a single microcontroller ADC pin, you can use four tri-state buffers. Tie all their outputs together, and use GPIO pins to toggle the OE pins, ensuring only one buffer is active at a time.

Tri-State vs. Open-Drain: The Common Confusion

The most common mistake hobbyists make is confusing tri-state outputs with open-drain (or open-collector) outputs. Both can 'disconnect' from a bus, but they do it differently and are used for entirely different protocols.

Feature	Tri-State Buffer	Open-Drain Output
HIGH State	Actively drives VCC (Strong HIGH)	Relies on external pull-up resistor (Weak HIGH)
LOW State	Actively drives GND (Strong LOW)	Actively drives GND (Strong LOW)
Disconnect State	Hi-Z (Both transistors OFF)	Hi-Z (NMOS OFF)
Primary Use Case	SPI, Parallel buses, high-speed data	I2C, shared interrupt lines, wired-AND logic
Speed Limitation	Limited by transistor switching time (Very Fast)	Limited by RC time constant of pull-up resistor (Slower)

If you are building an I2C bus, do not use tri-state buffers; use open-drain configurations. I2C relies on the wired-AND nature of open-drain lines for clock stretching and arbitration. If you are building an SPI bus or a parallel data bus, you must use tri-state logic.

Decision Path: Which Buffer Topology Do You Need?

Use this decision tree to select the exact part for your workbench.

If your circuit needs to...	Then use...	Concrete Part Pick
Share a high-speed SPI MISO line or parallel data bus	Tri-State Buffer	SN74LVC1G125 (Single) or 74HC125 (Quad)
Share an I2C bus, SMBus, or shared interrupt line	Open-Drain / Pull-up	PCA9306 (if level shifting) or configure MCU GPIO as Open-Drain
Level-shift a 3.3V SPI signal to 5V while maintaining Hi-Z	Tri-State with 5V VCC	SN74LVC1G125 (Powered at 5V, accepts 3.3V logic input)
Switch analog sensor signals to a single ADC pin	Analog Multiplexer	CD74HC4067 (16-channel) or TS5A3159 (Single SPDT)

Frequently Asked Questions