Static RAM (SRAM) is a type of volatile semiconductor memory that uses bistable latching circuitry (flip-flops) to store each bit, retaining data as long as power is applied without needing periodic refresh cycles. In a real circuit, choosing SRAM over DRAM eliminates the need for a dedicated memory controller to handle row-refresh cycles, simplifying your PCB timing and firmware, but it drastically increases your silicon area, pin count, and cost per megabyte. The most common bench mistake is assuming the word 'static' means non-volatile like Flash; SRAM loses its contents the millisecond VCC drops, and the term merely refers to the absence of a dynamic refresh clock.
The 6T Flip-Flop and Silicon Real Estate
To understand why SRAM is fast but physically massive, you have to look at the cell level. A single bit of Static RAM is typically built using a 6-transistor (6T) CMOS cell. Four transistors form two cross-coupled inverters that latch a 1 or 0, while two additional access transistors connect the cell to the bit lines during read and write operations.
Because there is no capacitor to leak charge, the 6T cell holds its state indefinitely as long as VCC is present. This eliminates the let-through current spikes and refresh overhead associated with DRAM, but it restricts SRAM to niche, low-capacity applications where speed and deterministic timing outweigh the cost per megabyte.
The Math: Bus Timing and Access Time Calculations
When wiring external SRAM to a microcontroller, the datasheet's 'access time' (tAA) dictates your bus throughput. Let us run a real-world timing calculation using an STM32H7 running its Flexible Memory Controller (FMC) at 100 MHz (a 10 ns clock period) and interfacing with a legacy 45 ns SRAM, such as the Infineon CY62167G.
1. Clock Period: 100 MHz = 10 ns per HCLK cycle.
2. SRAM Access Time (tAA): 45 ns (time from address valid to data valid).
3. DATAST Calculation: The FMC DATAST phase must cover the 45 ns access time. 45 ns / 10 ns = 4.5 cycles. Since the FMC register value is (cycles - 1), we program DATAST = 4 (yielding 5 actual cycles).
4. Total Read Cycle: ADDSET (1 cycle) + DATAST (5 cycles) + 1 internal cycle = 7 cycles total.
5. Effective Bus Time: 7 cycles × 10 ns = 70 ns per read.
6. Throughput on 16-bit Bus: 16 bits / 70 ns = 228 Mbits/s, or 28.5 MB/s.
If you swap that 45 ns chip for a 10 ns SRAM like the ISSI IS61WV102416, your DATAST drops to 0 (1 cycle), collapsing the read time to roughly 3 cycles (30 ns) and pushing throughput past 66 MB/s. This is why paying the premium for 10 ns SRAM is mandatory when buffering high-speed ADCs on modern 32-bit microcontrollers.
Where You Meet SRAM in Practice
You will rarely see discrete SRAM chips on consumer motherboards, but it is ubiquitous in embedded systems and high-performance computing architectures.
- CPU Caches (L1/L2/L3): Processors use SRAM for on-die caches because the 6T cell's read speed (sub-nanosecond) can keep up with multi-GHz core clocks, which DRAM cannot.
- FPGA Block RAM (BRAM): When you instantiate a memory block in Verilog or VHDL, the synthesizer maps it to dedicated SRAM hard-macros on the FPGA die for zero-latency local storage.
- Battery-Backed IoT Logging: In smart meters and industrial PLCs, a small 1 Mbit SRAM paired with a 3V lithium coin cell and a supervisory chip preserves critical state variables during brownouts.
- High-Speed Data Acquisition: Oscilloscopes and software-defined radios use SRAM as a circular buffer to catch transient microsecond events before a slower DMA controller moves the data to Flash or DRAM.
Memory Selection Decision Tree
Do not default to SRAM just because it is easier to wire. Use this decision matrix to select the correct memory topology for your 2026 PCB design.
| System Condition | Memory Type | Concrete Part Pick (2026) | Approx. Cost |
|---|---|---|---|
| Need >512 MB to run Linux or buffer video frames | DRAM (DDR3/DDR4) | Micron MT41K256M16 (4Gbit) | $6.50 |
| Need non-volatile logging that survives instant power loss | FRAM or NOR Flash | Cypress CY15B108QN (8Mbit FRAM) | $12.00 |
| Need fast, deterministic random-access buffer <16 MB, simple routing | SRAM | ISSI IS61WV102416 (16Mbit, 10ns) | $4.50 |
Wiring and Decoupling External SRAM
When laying out an external SRAM on a 4-layer PCB, signal integrity is your primary adversary. A 16-bit data bus switching simultaneously at 100 MHz generates massive ground bounce if decoupling is inadequate.
- Decoupling: Place a 100 nF X7R ceramic capacitor within 2 mm of every single VCC pin on the SRAM package. Do not rely on a single bulk capacitor at the end of the power rail.
- Series Termination: If your trace lengths exceed 2 inches (50 mm), add 22 Ω to 33 Ω series termination resistors on the address and control lines (WE#, OE#, CE#) close to the microcontroller to dampen reflections.
- Ground Planes: Route the 16-bit data bus over a solid, unbroken ground plane on Layer 2. Never route high-speed memory traces across split planes or near board cutouts.
Frequently Asked Questions
Can I use SRAM without a battery backup?
Yes, but only as a volatile scratchpad. If VCC drops below the SRAM's minimum retention voltage (usually around 2.0V for 3.3V parts), the flip-flops will collapse and the data is irretrievably lost. If you need data to survive a power cycle, you must use FRAM, EEPROM, or Flash.
Why do some SRAM chips have a 'byte enable' (LB#/UB#) pin?
On 16-bit SRAMs, the Lower Byte and Upper Byte pins allow the microcontroller to write to just 8 bits of the 16-bit word without performing a read-modify-write cycle. This saves bus cycles and simplifies firmware when handling standard 8-bit char arrays in C/C++.
What is the difference between asynchronous and synchronous SRAM?
The discrete chips discussed here (like the IS61WV series) are asynchronous; they respond to address and control pin changes immediately without a clock signal. Synchronous SRAM (like ZBT or QDR SRAM) uses a clock edge to latch addresses and data, allowing for pipelined bursting at multi-hundred-megahertz speeds, but requires a much more complex memory controller typically found only in FPGAs or networking ASICs.
