Resonance in a circuit occurs when the inductive reactance ($X_L$) and capacitive reactance ($X_C$) are equal in magnitude but exactly 180 degrees out of phase. At this specific resonant frequency ($f_r$), the reactive components cancel each other out, and the circuit behaves as a purely resistive load. In practical design, this phenomenon is the foundation of RF tuning, bandpass filtering, and impedance matching. Rather than treating resonance as an abstract textbook formula, this guide breaks down the physical topology, real-world component selection, and bench-testing protocols required to build a functional resonant network.
The Core Topology: Series vs. Parallel RLC Networks
To understand series resonance, we must first define the physical node layout of the circuit. In a standard Series RLC topology, the components are daisy-chained in a single current path:
- Node A (Vin): AC signal source input.
- Node B: Junction between the Resistor (R) and Inductor (L).
- Node C: Junction between the Inductor (L) and Capacitor (C).
- Node D (GND): Ground reference, completing the circuit through the Capacitor.
In contrast, a Parallel RLC topology connects all three components across the same two shared nodes (Node Top and Node Bottom), creating three separate current branches.
Why Choose Series Over Parallel?
The choice between series and parallel topologies depends entirely on the impedance profile you need at the resonant frequency. A series RLC circuit presents minimum impedance at $f_r$, allowing maximum current to flow from source to ground. This makes it the mandatory choice for bandpass filters, where you want a specific frequency to pass through to the load while attenuating others. A parallel RLC circuit presents maximum impedance at $f_r$, acting as a band-stop (notch) filter or an LC tank circuit for oscillators. For this design walkthrough, we will focus on the series topology, as it is the most common configuration for signal filtering and RF front-end matching.
Design Walkthrough: Building a 100 kHz Series Resonant Filter
Let’s design a series resonant bandpass filter targeting a center frequency ($f_r$) of 100 kHz. The governing equation for resonant frequency is:
$$f_r = \frac{1}{2\pi\sqrt{LC}}$$
Step 1: Select the Capacitor (C)
Inductors are physically larger, more expensive, and suffer from higher parasitic resistance than capacitors. Therefore, we pick a standard capacitor value first. Let’s choose a 1 nF (1000 pF) C0G/NP0 ceramic capacitor, such as the Kemet C315C102K5G5TA. C0G dielectrics are critical here; X7R or Y5V ceramics exhibit severe capacitance drift with applied voltage and temperature, which will detune your resonant peak.
Step 2: Calculate the Inductor (L)
Rearranging the formula to solve for L:
$$L = \frac{1}{(2\pi \cdot 100,000)^2 \cdot 1 \times 10^{-9}} \approx 2.53 \text{ mH}$$
We will select the closest standard value: a 2.5 mH axial inductor, such as the Bourns 78F2R5K-RC. This part has a DC resistance (DCR) of roughly 3.5 Ω, which we must account for in our Q-factor calculations.
Step 3: Set the Q-Factor with the Resistor (R)
The Quality factor (Q) determines the bandwidth and sharpness of the resonant peak. The formula for a series RLC circuit is:
$$Q = \frac{1}{R_{total}}\sqrt{\frac{L}{C}}$$
If we want a moderately sharp filter with a Q of 10, we solve for $R_{total}$:
$$R_{total} = \frac{1}{10}\sqrt{\frac{2.5 \times 10^{-3}}{1 \times 10^{-9}}} = 0.1 \cdot 1581 \approx 158 \text{ } \Omega$$
Since the inductor already contributes 3.5 Ω of DCR, our external resistor needs to be roughly 154.5 Ω. We will use a standard 150 Ω 1/2W metal film resistor (e.g., Vishay PR02), yielding a final circuit Q of approximately 10.3.
Every physical inductor has parasitic winding capacitance. This creates a parallel self-resonant frequency (SRF). If your target $f_r$ is too close to the inductor's SRF, the component will stop behaving like an inductor and start acting like a capacitor. Always check the manufacturer datasheet to ensure the SRF is at least 5 to 10 times higher than your target operating frequency.
Behavior Matrix & Extreme Failure Modes
Understanding how component drift affects the circuit is just as important as the initial design. The following matrix details the behavioral shifts when individual parameters change, followed by a critical contrast of failure modes.
| Parameter Changed | Effect on Resonant Freq ($f_r$) | Effect on Q-Factor | Effect on Bandwidth |
|---|---|---|---|
| Increase R | No change | Decreases (peak flattens) | Widens |
| Increase L | Decreases ($f_r \propto 1/\sqrt{L}$) | Increases | Narrows |
| Increase C | Decreases ($f_r \propto 1/\sqrt{C}$) | Decreases | Widens |
Failure Mode Contrast: Series vs. Parallel Topologies
When troubleshooting a dead board, you must know how open and short failures manifest differently depending on the topology. According to electronics design principles, the current paths dictate the failure result:
- Capacitor Shorts: In a series circuit, a shorted capacitor removes the DC blocking path, turning the network into an RL low-pass filter and potentially allowing destructive DC current to flow from the source. In a parallel circuit, a shorted capacitor shorts the entire tank, dropping the impedance across the nodes to zero and likely tripping the source protection or blowing a upstream fuse.
- Inductor Opens: In a series circuit, an open inductor breaks the single current path entirely; the circuit passes zero signal at all frequencies. In a parallel circuit, an open inductor simply removes the inductive branch, leaving a functional RC network that will pass high frequencies but lose its resonant tuning entirely.
- Resistor Opens: In series, an open R kills the circuit. In parallel, an open R (if placed in series with the source feeding the tank) kills the signal, but if the R is in parallel with L and C, an open R simply removes the damping, causing the Q-factor to spike to the limit of the component parasitics.
Breadboard Testing Protocol: Step-by-Step Verification
Simulations like LTspice assume ideal components. Physical breadboarding reveals the parasitics. Here is the exact bench procedure to verify your 100 kHz series RLC design using a function generator (e.g., Siglent SDG1032X) and an oscilloscope (e.g., Rigol DS1054Z).
- Prep the Breadboard: Insert the 150 Ω resistor, 2.5 mH inductor, and 1 nF capacitor in a single series row. Ensure the inductor is oriented away from any grounded planes to minimize stray capacitance.
- Establish Grounding: Connect the ground clip of your oscilloscope probe and the black banana jack of your function generator to the free leg of the capacitor (Node D). Keep ground leads under 2 inches to prevent ground-loop inductance from skewing the 100 kHz reading.
- Inject the Signal: Connect the function generator output to Node A (the free leg of the resistor). Set the generator to output a 2 Vpp sine wave with a 0V DC offset.
- Probe the Output: Attach your oscilloscope probe (set to 10X attenuation) to Node C (the junction between the inductor and capacitor). This measures the voltage across the capacitor, which will peak at resonance.
- Execute the Frequency Sweep: Start at 10 kHz. Slowly increase the frequency in 5 kHz increments. Watch the oscilloscope amplitude. As you approach 100 kHz, the voltage amplitude will rise sharply.
- Identify the Peak and -3dB Points: Note the exact frequency where the peak voltage occurs (your actual $f_r$). Record the peak voltage ($V_{max}$). Calculate $V_{max} \times 0.707$ (the -3dB point). Sweep down in frequency to find the lower cutoff ($f_L$) and sweep up to find the upper cutoff ($f_H$). Your bandwidth is $f_H - f_L$, and your measured Q is $f_r / \text{Bandwidth}$.
Frequently Asked Questions
What is resonance in a circuit used for practically?
Beyond textbook exercises, resonance is the operating principle behind AM/FM radio tuners, where a variable capacitor shifts the $f_r$ of an LC tank to isolate a specific broadcast frequency. It is also used in induction heating, where a high-Q parallel resonant circuit generates massive circulating currents to heat metals, and in RFID tags, where the reader and tag coils are tuned to the same resonant frequency (typically 13.56 MHz) to maximize inductive power transfer.
How does parasitic capacitance affect high-frequency resonance?
At frequencies above 10 MHz, the stray capacitance between breadboard contacts, component leads, and PCB traces (often 2pF to 5pF) begins to parallel your intentional capacitor. If your design calls for a 10 pF capacitor, 3 pF of stray capacitance will shift your resonant frequency downward by over 13%. At RF frequencies, you must use surface-mount components (SMD) on a properly laid-out PCB with controlled impedance traces, and account for pad capacitance in your simulation.
Why does my resonant peak look flat on the oscilloscope?
A flat or heavily damped peak indicates a lower-than-expected Q-factor. This is almost always caused by unaccounted series resistance. Check your inductor's DC resistance (DCR); if you are using a small, cheap inductor, the DCR might be 20 Ω, which will crush the Q-factor of a low-impedance design. Additionally, verify that your oscilloscope probe is properly compensated and that your function generator's 50 Ω output impedance isn't inadvertently acting as part of your series R, dampening the circuit.
What is the difference between series and parallel resonance?
The fundamental difference lies in impedance at the resonant frequency. In a series resonant circuit, $X_L$ and $X_C$ cancel out, leaving only the resistance, resulting in minimum impedance and maximum current draw from the source. In a parallel resonant circuit, the circulating current between the inductor and capacitor is maximized, but the current drawn from the external source drops to a minimum, resulting in maximum impedance. Series is used to pass a specific frequency (bandpass); parallel is used to block a specific frequency (notch) or store energy (tank).
