Morgan's Law (formally known as De Morgan's Laws) is a pair of Boolean algebra theorems stating that inverting the output of an AND gate yields the exact same logical result as an OR gate with inverted inputs, and vice versa. If you are asking "what is Morgan's law" while staring at a schematic, a PCB layout, or a PLC ladder diagram, you are looking at the mathematical justification for swapping gate types to save silicon, reduce propagation delay, or simplify physical relay wiring. It is the bridge between abstract boolean math and physical hardware optimization.
The Core Formulas and What They Change in Real Circuits
De Morgan's Laws are defined by two primary equations:
- Rule 1: The complement of a product is equal to the sum of the complements.
NOT (A AND B) = (NOT A) OR (NOT B) - Rule 2: The complement of a sum is equal to the product of the complements.
NOT (A OR B) = (NOT A) AND (NOT B)
When designing with standard 74-series logic or discrete MOSFETs, you rarely have the exact gate you need in your current IC package. Morgan's Law lets you "push bubbles" (inversion circles) through logic gates, changing an AND into an OR (or vice versa) as long as you invert the inputs and the output. This turns a multi-chip nightmare into a single-chip solution.
Worked Numeric Example: Optimizing a 74HC-Series BOM
Let's look at a concrete hardware scenario. You are designing a safety interlock circuit for a 2026 CNC router. The spindle must not engage unless both the Door Sensor (A) and the Coolant Sensor (B) are active. The logic required is Y = NOT (A AND B) (active-low enable).
The Naive Approach:
You implement this exactly as written. You use a 74HC08 (Quad 2-input AND gate) to combine A and B, then route that into a 74HC04 (Hex Inverter) to flip the output.
- ICs Required: 74HC08 + 74HC04
- BOM Cost: ~$0.35 + ~$0.30 = $0.65
- Propagation Delay (tpd): 18ns (AND) + 14ns (NOT) = 32ns total
The Morgan's Law Approach:
Apply Rule 1: NOT (A AND B) is logically identical to a single NAND gate. You drop the inverter and the AND chip, replacing both with a single 74HC00 (Quad 2-input NAND gate).
- ICs Required: 74HC00 only
- BOM Cost: $0.32
- Propagation Delay (tpd): 18ns total
Where You Meet This in Practice
You will encounter the practical necessity of Morgan's Law in three distinct areas of electrical and electronic engineering:
1. PCB Design and Universal Logic
NAND and NOR gates are "universal gates." Using Morgan's Law, you can build any logic function (AND, OR, XOR, NOT) using only NAND gates or only NOR gates. In high-volume manufacturing, stocking a single part number (like the 74HC00 NAND) for all basic logic needs reduces supply chain friction and allows you to use the spare gates in a quad-package for other tasks on the board, rather than leaving them floating.
2. PLC Ladder Logic and Safety Wiring
In industrial automation, physical wiring often dictates logic. Consider an emergency stop circuit with two E-Stop buttons. You want the motor to stop if E-Stop 1 OR E-Stop 2 is pressed: Motor_Run = NOT (E1 OR E2).
Wiring two normally-open (NO) switches in parallel and feeding them into a NOT instruction works in software, but it fails the "fail-safe" test if a wire breaks. Using Morgan's Law, we rewrite this as Motor_Run = (NOT E1) AND (NOT E2). In physical terms, this means wiring two normally-closed (NC) switches in series. If a wire breaks, the circuit opens, and the motor stops safely. Morgan's Law is the mathematical proof that allows us to convert unsafe parallel NO logic into safe series NC logic.
3. Embedded C/C++ Firmware Optimization
When writing bitwise operations for microcontrollers like the STM32 or ESP32, complex conditional statements can eat up CPU cycles. Compilers are smart, but manually applying De Morgan's theorems to bitwise masks (e.g., ~(A & B) == ~A | ~B) can sometimes help you structure register configurations more cleanly, especially when setting or clearing specific bits in a hardware peripheral register.
Decision Tree: When and How to Apply Morgan's Law
Use this decision path to determine exactly which component or logic structure to pick when faced with a design constraint.
| Design Constraint / Symptom | Diagnostic Question | Morgan's Law Action | Concrete Pick / Implementation |
|---|---|---|---|
| Out of AND gates on PCB, but have spare NOR gates | Can I invert the inputs and output of the available gate? | Convert AND to NOR by inverting all inputs and the final output. | Use 74HC02 (Quad NOR). Wire inputs through inverters or use active-low signals. |
| PLC safety circuit uses parallel NO contacts (OR logic) | Does a broken wire cause a dangerous failure-to-run state? | Apply Rule 2 to convert OR logic into series AND logic with inverted physical states. | Rewire field devices to Normally Closed (NC) contacts in series. Update PLC to use AND (XIC) instructions. |
| Propagation delay is too high for a high-speed clock divider | Am I chaining an AND/OR gate directly into a NOT gate? | Combine the two stages into a single universal gate stage. | Replace 74HC08 + 74HC04 with a single 74HC00 (NAND) or 74HC02 (NOR). |
| Firmware bitwise mask is overly complex to read | Am I using nested negations like ~(~A | ~B)? |
Push the negations inward to simplify the C syntax. | Rewrite as (A & B). Use standard AND (&) bitwise operators. |
Common Confusions and Mistakes to Avoid
When applying these theorems on the bench or in software, hobbyists and junior engineers frequently make two specific errors:
When you "push a bubble" (an inversion) through a gate, the gate type must change. An AND becomes an OR; an OR becomes an AND. If you invert the inputs of an AND gate but leave it as an AND gate, you have not applied Morgan's Law—you have just created a completely different truth table.
Mistake 2: Confusing it with the Distributive Law.
Morgan's Law deals strictly with inversions (NOT) interacting with AND/OR. The Distributive Law (A AND (B OR C) = (A AND B) OR (A AND C)) deals with expanding terms. If there are no inversion bubbles or NOT operators involved in your simplification step, you are using distribution, not De Morgan's.
Mistake 3: Leaving floating inputs on unused gates.
When you optimize your BOM using Morgan's Law and consolidate chips, you often end up with unused gates in a quad-package. Never leave the inputs of unused CMOS gates (like the 74HC series) floating. A floating input will oscillate at high frequencies due to ambient EMI, causing the chip to overheat and draw excessive current. Always tie unused inputs to VCC or GND.
FAQ: Morgan's Law in Digital Design
Q: Does Morgan's Law apply to analog circuits?
A: No. Morgan's Law is strictly a theorem of Boolean algebra, which governs discrete digital logic (1s and 0s). In analog design, you deal with continuous voltages and Kirchhoff's laws, not Boolean inversions.
Q: Why is it called Morgan's Law instead of De Morgan's Law?
A: It is formally "De Morgan's Laws," named after mathematician Augustus De Morgan. However, in quick search queries, bench shorthand, and some regional textbooks, it is frequently truncated to "Morgan's Law." The mathematical application remains identical.
Q: Can I use Morgan's Law to simplify a 3-input gate?
A: Yes, the theorems scale to any number of variables. For example, NOT (A AND B AND C) = (NOT A) OR (NOT B) OR (NOT C). This is highly useful when designing custom discrete transistor logic (like RTL or DTL) where 3-input ICs might be unavailable, allowing you to build the equivalent using multiple 2-input NOR/NAND gates.
For further reading on Boolean optimization, refer to the All About Circuits digital textbook chapter on De Morgan's Theorems, or consult standard logic design references like the Electronics Tutorials guide on Boolean Algebra. When selecting physical ICs, always verify propagation delays and supply voltage ranges in the manufacturer's specific datasheet (e.g., Texas Instruments SN74HC series) before finalizing your BOM.
