What Is an LC Circuit? Topology, Resonance, and Real-World Design

An LC circuit (inductor-capacitor circuit) is a resonant electrical network where energy oscillates continuously between the magnetic field of an inductor (L) and the electric field of a capacitor (C). The core governing equation for its resonant frequency is f_r = 1 / (2π√LC). When driven at this exact frequency, the reactive impedances of the two components cancel each other out, resulting in extreme circuit behaviors depending on how they are wired. In practical RF design, power electronics, and intermediate frequency (IF) filtering, understanding what an LC circuit is goes far beyond the textbook formula; it requires managing real-world parasitics like equivalent series resistance (ESR) and self-resonant frequency (SRF).

Series vs. Parallel LC Topology & Node Mapping

To design with LC networks, you must first choose between the two fundamental topologies: series and parallel (often called a tank circuit). Both share a basic three-node mapping:

• Node A (Input/Drive): The signal source or voltage injection point.
• Node B (Junction): The electrical connection point between the inductor and the capacitor.
• Node C (Ground/Return): The common reference plane.

In a series LC topology, the inductor and capacitor are daisy-chained between Node A and Node C, with Node B acting as the output tap. At resonance, their impedances cancel, creating a near-short circuit (limited only by parasitic resistance). We use series LC circuits for bandpass filters, notch filters (when placed in a shunt path), and series-fed antenna matching networks.

In a parallel LC topology, both the inductor and capacitor share Node A on one side and Node C on the other. Node B is effectively the top rail. At resonance, the circulating current between L and C is massive, but the current drawn from the source drops to near zero. This creates a near-open circuit (high impedance). We choose the parallel topology over the series alternative when we need high-impedance bandstop filters, LC oscillator tanks (like in Colpitts or Hartley oscillators), or induction heating work coils, because the high impedance allows for high voltage gain and sustained oscillation with minimal drive current.

Component Behavior & Parameter Shift Matrix

When tuning an LC network on the bench, changing a single parameter cascades through the circuit's behavior. The table below maps exactly what happens to the resonant frequency, impedance at resonance, and Quality factor (Q) when you alter component values or encounter parasitic shifts.

Parameter Changed	Effect on Resonant Frequency (fr)	Parallel Impedance at fr	Series Impedance at fr	Effect on Q-Factor
Increase Inductance (L)	Decreases	Increases (if R is constant)	Unchanged (dominated by R)	Increases (Parallel) / Decreases (Series)
Increase Capacitance (C)	Decreases	Decreases	Unchanged (dominated by R)	Decreases (Parallel) / Increases (Series)
Increase Inductor DCR (Wire Resistance)	Unchanged	Decreases sharply	Increases	Decreases (Both topologies)
Increase Capacitor ESR (Dielectric Loss)	Unchanged	Decreases	Increases	Decreases (Both topologies)
Approach Inductor SRF (Parasitic Capacitance)	Skews higher than calculated	Collapses (becomes capacitive)	Spikes unpredictably	Degrades severely

According to fundamental AC theory outlined by All About Circuits, the Q-factor of a parallel tank is roughly R / X_L, meaning any increase in the parallel resistance (or reduction in inductor wire resistance) boosts the Q, resulting in a sharper, narrower resonance peak.

Design Walkthrough: Building a 100 kHz Tank Circuit

Let's design a parallel LC tank circuit targeting a 100 kHz resonant frequency for use in a basic AM radio IF stage or a low-frequency RFID reader front-end.

Step 1: Select the Capacitor (C)
We need a stable capacitance that won't drift with temperature or applied voltage. Never use X7R or Y5V ceramics for resonant tanks; their piezoelectric microphonics and voltage coefficient will detune your circuit under signal load. We select a 10 nF (0.01 µF) C0G/NP0 ceramic capacitor (e.g., Vishay VJ103K15C0G). C0G dielectrics offer near-zero temperature drift.

Step 2: Calculate the Inductor (L)
Rearranging the resonance formula to solve for L:
L = 1 / [ (2π × f_r)² × C ]
L = 1 / [ (2π × 100,000)² × 10 × 10⁻⁹ ]
L = 1 / [ 3.947 × 10¹¹ × 10⁻⁸ ] = 253.3 µH

Step 3: Select the Real-World Inductor
Standard values don't always hit the exact calculated number. We select the Wurth Elektronik 744774251, a shielded surface-mount power inductor rated at 250 µH with a low DC resistance (DCR) of 0.65 Ω and a saturation current of 1.2 A. Crucially, its Self-Resonant Frequency (SRF) is rated at 2.8 MHz, which is well above our 100 kHz target, ensuring the inductor behaves inductively and not capacitively at our operating point.

Step 4: Verify the Actual Resonant Frequency
Using the real 250 µH value:
f_r = 1 / (2π × √(250 × 10⁻⁶ × 10 × 10⁻⁹)) = 100.65 kHz.
This 0.65% deviation is well within standard component tolerances (typically ±5% to ±10% for inductors).

Failure Modes: What Breaks at the Extremes?

When troubleshooting or designing protection into LC networks, you must understand how the circuit behaves when a component fails open or short. The failure modes contrast sharply between series and parallel configurations.

Parallel LC (Tank) Extremes

• Inductor Shorts (DCR drops to near zero): The inductor becomes a dead short across the AC source. In a parallel topology, this pulls Node A directly to Node C (Ground). If driven by a low-impedance voltage source, this will draw massive current, likely destroying the driver transistor or blowing the source fuse. The resonant behavior is completely lost.
• Capacitor Opens: The capacitor is removed from the circuit. The network devolves into a simple inductor tied to ground. The high-impedance resonance peak vanishes, and the circuit becomes a low-pass RL filter (if source resistance is considered), rolling off at higher frequencies without any peaking.
• Capacitor Shorts: Similar to an inductor short, this creates a direct low-impedance path to ground at all frequencies, killing the resonance and potentially overloading the drive stage.

Series LC Extremes

• Inductor Opens: The signal path between Node A and Node B is broken. No current flows. The output at Node B drops to zero (or floats, depending on the load). The circuit fails completely safe (open).
• Capacitor Shorts: The capacitor becomes a wire. The inductor is now the only component in the series path. The circuit loses its bandpass resonance and becomes a simple high-pass RL filter, passing high frequencies while blocking DC and low frequencies via the inductor's reactance.
• Inductor Shorts: The inductor becomes a wire. The circuit becomes a simple high-pass RC filter, passing high frequencies through the capacitor while blocking DC.

For deeper mathematical proofs on how these open/short faults alter the complex impedance plane, reference the Electronics Tutorials guide on parallel resonance.

Step-by-Step Breadboard Verification

Theory and datasheets only get you so far. To verify the 100 kHz tank circuit designed above, you need to measure it on the bench. Here is the exact procedure using a standard hobbyist/prosumer setup (e.g., Siglent SDG1032X function generator and a Rigol DS1054Z oscilloscope).

1. Wire the Tank with Parasitics in Mind: Insert the 250 µH radial inductor and 10 nF ceramic capacitor into adjacent rows on a solderless breadboard. Keep the lead lengths as short as physically possible. At 100 kHz, long breadboard jumper wires introduce stray inductance (roughly 10 nH per cm) and stray capacitance to the ground plane, which will pull your resonant frequency down.
2. Configure the Function Generator: Set the Siglent generator to output a sine wave. Set the amplitude to 2 Vpp. Crucially, engage the High-Z (High Impedance) output mode in the generator's utility menu, or place a 10 kΩ resistor in series with the generator's output lead to prevent the generator's internal 50 Ω termination from damping the tank's Q-factor.
3. Set Up the Oscilloscope Sweep: Connect Channel 1 to the generator output (Node A) and Channel 2 to the tank junction (Node B). Set the timebase to 5 µs/div. Use the scope's built-in Bode plotter function (if available) or manually step the generator frequency from 50 kHz to 150 kHz in 2 kHz increments.
4. Identify the Peak and Phase Shift: Watch the amplitude of Channel 2. As you approach 100.6 kHz, the voltage at Node B will spike dramatically (potentially exceeding the 2 Vpp input due to the Q-factor voltage magnification). At the exact resonant peak, the phase difference between Channel 1 and Channel 2 should read exactly 0 degrees (the voltage and current are perfectly in phase, meaning the circuit looks purely resistive).
5. Measure the Bandwidth (-3 dB Points): Note the peak voltage (e.g., 10 Vpp). Calculate 70.7% of that peak (7.07 Vpp). Sweep the frequency down until the amplitude drops to 7.07 Vpp (f_low), and sweep up until it drops again (f_high). The bandwidth is f_high - f_low. Divide your center frequency (100.6 kHz) by this bandwidth to calculate the empirical Q-factor of your physical breadboarded circuit.

By understanding the node topology, respecting the parasitic limits of real components, and verifying the phase alignment on a scope, you transition from merely knowing what an LC circuit is to actively mastering RF and filter design on the bench.