A full adder is a combinational logic circuit that adds three single-bit binary inputs (A, B, and a Carry-In) to produce a two-bit binary output consisting of a Sum and a Carry-Out. While basic logic gates handle single Boolean operations, the full adder is the fundamental building block that allows digital systems to perform multi-bit arithmetic by passing overflow states from one bit position to the next.
The Core Logic: Truth Table and Gate Implementation
To understand what a full adder changes in a real circuit, you have to look at the inputs. A basic adder only looks at two bits. But in multi-bit math, the previous column's overflow (the carry) must be added to the current column. The full adder solves this by introducing a third input: Cin (Carry-In).
The Boolean algebra governing the outputs is straightforward but critical for timing analysis:
- Sum (S): $S = A \oplus B \oplus C_{in}$ (The output is HIGH if an odd number of inputs are HIGH).
- Carry-Out (Cout): $C_{out} = (A \cdot B) + (C_{in} \cdot (A \oplus B))$ (A carry is generated if both A and B are HIGH, or if the incoming carry meets a single HIGH input).
| A | B | Cin | Sum | Cout | Decimal Equivalent |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 + 0 + 0 = 0 |
| 0 | 0 | 1 | 1 | 0 | 0 + 0 + 1 = 1 |
| 0 | 1 | 0 | 1 | 0 | 0 + 1 + 0 = 1 |
| 0 | 1 | 1 | 0 | 1 | 0 + 1 + 1 = 2 |
| 1 | 0 | 0 | 1 | 0 | 1 + 0 + 0 = 1 |
| 1 | 0 | 1 | 0 | 1 | 1 + 0 + 1 = 2 |
| 1 | 1 | 0 | 0 | 1 | 1 + 1 + 0 = 2 |
| 1 | 1 | 1 | 1 | 1 | 1 + 1 + 1 = 3 |
Worked Numeric Example: 4-Bit Ripple Carry Addition
Let's move from theory to the bench. Suppose you are building a 4-bit calculator using a Texas Instruments SN74LS283 4-bit binary full adder IC. You want to add 13 (Binary 1101) and 6 (Binary 0110).
The SN74LS283 internally cascades four full adders. We tie the initial Carry-In (C0) to Ground (Logic 0). Here is how the carry propagates through the silicon, bit by bit, from Least Significant Bit (LSB) to Most Significant Bit (MSB):
- Bit 0 (1s place): A=1, B=0, Cin=0. Sum = 1. Cout = 0.
- Bit 1 (2s place): A=0, B=1, Cin=0 (from previous). Sum = 1. Cout = 0.
- Bit 2 (4s place): A=1, B=1, Cin=0. Sum = 0. Cout = 1.
- Bit 3 (8s place): A=1, B=0, Cin=1 (from previous). Sum = 0. Cout = 1.
The Result: Reading the final Carry-Out and the Sums from MSB to LSB, we get 10011. In decimal, this is 19 (16 + 2 + 1). The math checks out: 13 + 6 = 19. This example highlights the primary job of the full adder: routing that critical Bit 2 carry into the Bit 3 calculation. Without the Cin pin, the Bit 3 calculation would incorrectly yield 1 instead of 0, breaking the entire operation.
Where You Meet This in Practice
You rarely wire discrete XOR and AND gates to build a full adder on a modern PCB, but the architecture is everywhere in digital design:
- Microcontroller ALUs: The Arithmetic Logic Unit inside an Arduino's ATmega328P or an ARM Cortex-M0 relies on banks of full adders to execute
ADDandADC(Add with Carry) assembly instructions. - FPGA Carry Chains: If you program an FPGA (like a Xilinx Artix-7), you shouldn't instantiate standard logic gates for math. The silicon features dedicated hard-macro carry chains (like the
CARRY4primitive) that route the Cout directly to the next block's Cin via specialized, ultra-fast routing wires, bypassing general programmable interconnects. - BCD (Binary Coded Decimal) Correction: When driving 7-segment displays, standard binary addition fails at 10. A full adder circuit is often paired with a comparator that detects sums greater than 9, automatically adding
0110(6) to force the binary result back into valid BCD format.
Full Adder vs. Half Adder: Clearing the Confusion
The most common mistake students and junior technicians make is confusing the full adder with the half adder. A half adder only has two inputs (A and B) and no Carry-In.
| Feature | Half Adder | Full Adder |
|---|---|---|
| Inputs | 2 (A, B) | 3 (A, B, Cin) |
| Outputs | 2 (Sum, Cout) | 2 (Sum, Cout) |
| Gate Count (Standard) | 2 (1 XOR, 1 AND) | 5 (2 XOR, 2 AND, 1 OR) |
| Cascadable? | No (drops incoming carry) | Yes (passes carry to next stage) |
| Use Case | Only useful for the very first LSB bit | Required for all subsequent bits in multi-bit math |
Frequently Asked Questions
What is the difference between a half adder and a full adder?
A half adder adds two single bits and produces a sum and a carry, but it cannot accept a carry from a previous operation. A full adder adds three bits (two data bits plus a carry-in), allowing it to be daisy-chained (cascaded) to add numbers of any bit width. In a multi-bit ripple carry adder, you might use a half adder for the very first LSB position to save a gate, but every subsequent bit requires a full adder.
How many NAND gates does it take to build a full adder?
If you are restricted to using only universal NAND gates (common in ASIC design or when you only have a 74HC00 quad-NAND IC on your bench), it takes a minimum of 9 NAND gates to implement a single full adder. This is a classic digital logic interview question and a great exercise in Boolean minimization using De Morgan's laws.
Why do modern CPUs use carry-lookahead instead of ripple carry full adders?
In a standard 'ripple carry' architecture, the carry must sequentially propagate through every full adder. If you are adding two 64-bit numbers, the 64th bit cannot resolve until the carry ripples through the previous 63 stages. At a propagation delay of 10ns per stage, that's 640ns of latency—a massive bottleneck for a multi-GHz CPU. Carry-lookahead adders (CLAs) use complex 'generate' and 'propagate' logic to calculate all carries simultaneously in parallel, reducing the delay to just a few gate levels regardless of bit width.
Can a full adder be used as a subtractor?
Yes. By utilizing 2's complement arithmetic, a full adder can perform subtraction without needing a dedicated subtractor circuit. To calculate A - B, you invert all the bits of B (using NOT gates or XOR gates tied to a control pin) and then tie the initial Carry-In (Cin) of the LSB full adder HIGH (Logic 1). The adder effectively computes A + (NOT B) + 1, which is the exact mathematical definition of 2's complement subtraction. This is exactly how the SUB instruction works in the ALU of your microcontroller.
