What Is Digital Audio? A Circuit-Level Guide to Sampling and I2S

Digital audio is the representation of continuous analog sound waves as a discrete sequence of binary numbers, captured by sampling the wave's amplitude at regular intervals and quantizing those measurements into specific bit values. When you move from analog audio design to digital, you stop worrying about thermal noise in op-amps and start worrying about clock jitter, quantization error, and digital bus impedance. This guide breaks down the exact math, the circuit-level implications, and a real bench scenario where digital audio goes wrong.

The Core Math: Sample Rate, Bit Depth, and the Nyquist Limit

To digitize a sound wave, an Analog-to-Digital Converter (ADC) takes rapid "snapshots" of the continuous voltage. The quality and bandwidth of that capture are governed by two strict parameters:

Sample Rate (Time Resolution): How many snapshots are taken per second. The Nyquist-Shannon sampling theorem dictates that to perfectly reconstruct a signal, your sample rate must be at least twice the highest frequency present in the analog signal. Since human hearing tops out around 20 kHz, a 44.1 kHz sample rate (the CD standard) captures up to 22.05 kHz, providing a small 2.05 kHz guard band for the analog anti-aliasing filter to roll off.

Bit Depth (Amplitude Resolution): How many discrete voltage levels each snapshot can be assigned to. A 16-bit system has 2^16 (65,536) possible levels. A 24-bit system has 2^24 (16,777,216) levels. Every additional bit yields roughly 6.02 dB of dynamic range.

Worked Numeric Example: Calculating I2S Data Throughput

Let's calculate the raw data rate required for a standard high-resolution stereo audio stream before any compression (like MP3 or FLAC) is applied. Assume we are streaming 2 channels (Stereo) at a 24-bit depth and a 96,000 Hz sample rate.

• Calculation: 2 channels × 24 bits × 96,000 samples/second = 4,608,000 bits per second.
• Result: 4.608 Mbps of continuous, real-time throughput.

If you are routing this over an I2S bus on a microcontroller, your Bit Clock (BCLK) must run at exactly 4.608 MHz to keep the data flowing without buffer underruns. If your MCU's clock divider can't hit that exact frequency, you will hear rhythmic clicking as the FIFO buffer starves.

What Digital Audio Changes in Your Circuit Design

In a purely analog circuit, a 1 kHz sine wave is a continuously varying voltage. If you pick up 60 Hz mains hum, it adds linearly to the waveform. Digital audio changes the physical reality of the circuit. The audio is now a stream of 1s and 0s represented by logic high (e.g., 3.3V) and logic low (0V) square waves. This shifts your design priorities entirely:

• Impedance Matching: High-speed digital audio buses like S/PDIF (coaxial) require strict 75-ohm impedance matching. If you use standard 50-ohm oscilloscope probes or mismatched RCA cables, signal reflections will cause data dropouts and harsh digital clipping.
• Clock Jitter: The timing of the clock signal (BCLK/LRCLK) must be incredibly precise. If the clock edge wanders by even a few picoseconds (jitter), the DAC will latch the digital data at the wrong micro-moment, translating timing errors back into analog amplitude noise. This is why audiophile DACs spend heavily on femtosecond crystal oscillators.
• Grounding Topography: Digital switching noise from a microcontroller or DSP is incredibly harsh. If your digital ground return path shares a trace with your analog DAC output ground, you will hear a harsh digital hash in the speakers. Star grounding or split ground planes with a single tie-point under the DAC chip are mandatory.

Where You Meet This in Practice (and Common Confusions)

What People Commonly Confuse It With

1. Sample Rate vs. Bit Depth: Makers often think "higher is always better" and max out both. But sample rate dictates frequency response (highs), while bit depth dictates dynamic range (the noise floor). Increasing sample rate from 44.1 kHz to 192 kHz does not make the audio "clearer" in the midrange; it just extends the ultrasonic bandwidth and makes your analog anti-aliasing filter design easier.
2. Digital Volume vs. Analog Gain: Turning down a 16-bit digital stream by 24 dB effectively destroys 4 bits of resolution, raising the noise floor and introducing quantization distortion. It is almost always better to keep the digital stream at 0 dBFS (full scale) and use an analog potentiometer or a digitally-controlled analog amplifier (like a PGA2311) for volume control.

Bench Scenario Walkthrough: Debugging a Noisy I2S DAC Output

Let’s look at a real-world failure mode when setting up digital audio on the bench, based on common issues documented in All About Circuits' ADC and DAC fundamentals.

The Setup:
You are building a wireless speaker using an ESP32 DevKit v1 and a MAX98357A I2S amplifier breakout board. You wire the ESP32's GPIO pins to the MAX98357A's BCLK, LRC (Word Select), and DIN pins using 6-inch Dupont jumper wires on a breadboard.

The Numbers:
You configure the ESP32 I2S driver for 16-bit depth and a 44.1 kHz sample rate. This requires a Bit Clock (BCLK) of 1.4112 MHz (2 channels × 16 bits × 44,100 Hz).

The Outcome:
When you play a 1 kHz test tone, the speaker outputs the correct pitch, but it is buried under a loud, high-frequency whine, and the audio randomly pops and drops out every few seconds.

What Went Wrong (and the Fix):

1. Clock Jitter from Long Wires: 6-inch unshielded jumper wires act as antennas at 1.4 MHz. The BCLK signal is ringing and overshooting, causing the MAX98357A to misread the clock edges. Fix: Keep I2S traces under 2 inches on a PCB, or use a twisted-pair cable for breadboard prototyping to minimize loop area.
2. Missing MCLK Configuration: The MAX98357A can generate its own Master Clock (MCLK) internally, but the ESP32's default I2S configuration was sending a poorly phased MCLK signal on a shared pin, confusing the amp's internal PLL. Fix: Tie the MAX98357A's MCLK pin to GND to force it to use its internal PLL, or explicitly configure the ESP32 i2s_pin_config_t struct to output a clean, dedicated MCLK.
3. Ground Loop Hash: The USB power for the ESP32 and the bench power supply for the speaker shared a messy ground path through the breadboard's power rails. Fix: Power both from the same regulated 5V bus and use a star-ground topology, tying the digital and analog grounds at a single point near the amplifier's bypass capacitors.

FAQ: Digital Audio on the Bench