If you hook a Fluke 87V multimeter to a 50-ohm microstrip trace, it will read near zero ohms. Yet, if you drive a 5 Gbps PCIe signal down that same trace, it behaves exactly like a 50-ohm resistor. When hardware engineers ask, "what is an impedance" in the context of signal integrity, they are not talking about DC resistance. They are asking about characteristic impedance ($Z_0$): the ratio of voltage to current of a traveling electromagnetic wave propagating along a transmission line.
In high-speed digital and RF design, ignoring $Z_0$ leads to catastrophic signal reflections, timing jitter, and failed EMC certifications. This guide breaks down the physics of trace impedance, identifies how noise couples into your signals, and provides a ranked list of fixes you can implement on your next PCB spin.
The Physics of Trace Impedance and Coupling Paths
Characteristic impedance is determined entirely by the physical geometry of the trace and the dielectric properties of the PCB substrate, not by the length of the wire. It is governed by the distributed inductance ($L$) and capacitance ($C$) per unit length: $Z_0 = \sqrt{L/C}$. A wider trace increases capacitance to the ground plane, which lowers the impedance. A thicker dielectric decreases capacitance, raising the impedance.
Below is a data-dense reference table for standard 1 oz copper FR-4 stackups. Use these baseline geometries when setting up your impedance calculator in Altium or KiCad.
| Trace Topology | Target $Z_0$ | Trace Width (W) | Dielectric Height (H) | Propagation Delay |
|---|---|---|---|---|
| Surface Microstrip | 50 Ω (Single) | 0.279 mm (11 mil) | 0.152 mm (6 mil) | ~145 ps/inch |
| Surface Microstrip | 100 Ω (Differential) | 0.127 mm (5 mil) / 0.127 mm gap | 0.152 mm (6 mil) | ~145 ps/inch |
| Embedded Stripline | 50 Ω (Single) | 0.114 mm (4.5 mil) | 0.101 mm (4 mil) | ~170 ps/inch |
| Embedded Stripline | 100 Ω (Differential) | 0.101 mm (4 mil) / 0.152 mm gap | 0.101 mm (4 mil) | ~170 ps/inch |
Identifying the Dominant Coupling Paths
When signal integrity degrades, noise is entering your circuit through one of three coupling paths. Identifying which path is dominant is critical for selecting the right fix:
- Conductive Coupling: Noise travels through shared physical conductors, most commonly a shared ground return path. This manifests as ground bounce when multiple signals switch simultaneously through a single, high-inductance via.
- Capacitive Coupling: Electric fields fringe between adjacent parallel traces. Which coupling path is dominant here? For high-speed digital edge rates (sub-nanosecond), capacitive coupling is the dominant path for Near-End Crosstalk (NEXT) between parallel routing layers.
- Radiated Coupling: The signal loop acts as an antenna. This is the dominant path for EMI failures when the ground plane beneath a trace is slotted or broken, forcing the return current to take a massive detour.
Ranked Fixes for Impedance Mismatches and Noise
When you have an impedance mismatch—say, a 50-ohm driver feeding a 75-ohm trace—the signal reflects at the boundary. The reflection coefficient ($\Gamma$) dictates how much voltage bounces back. To kill reflections and noise, apply these fixes in order of cost-effectiveness.
- Continuous Ground Plane (Cost: $0 BOM | Effectiveness: 95%)
The cheapest fix that actually works is ensuring an unbroken, solid ground plane directly beneath your signal layer. This provides a low-inductance return path, minimizes loop area (killing radiated EMI), and locks in your $Z_0$. Never route high-speed signals over plane splits. - Series Source Termination (Cost: $0.01 per resistor | Effectiveness: 90%)
For point-to-point topologies (like an SPI clock line), place a 22Ω to 33Ω resistor in series as close to the driver pin as possible. If the driver has an internal output impedance of 17Ω, adding a 33Ω external resistor brings the total source impedance to 50Ω, perfectly matching a 50Ω trace and absorbing reflections at the source. - Parallel / Thevenin Termination (Cost: $0.02 to $0.05 | Effectiveness: 85%)
For multi-drop buses or memory interfaces (like DDR4), terminate the far end of the trace to VTT or ground. This burns DC power and requires tighter routing, but it clamps the voltage at the receiver, eliminating ringing on long lines. - AC Coupling Capacitors (Cost: $0.02 | Effectiveness: Situational)
Used primarily to block DC common-mode offsets between transceivers (like PCIe or USB 3.0), typically using 100nF 0402 X7R capacitors placed near the receiver. They do not fix impedance mismatches but are mandatory for protocol compliance.
Proving the Fix: Before and After Measurement Methods
You cannot verify high-speed signal integrity with a standard digital multimeter. To prove your fix, you need to measure the signal's time-domain or frequency-domain response. According to Keysight's signal integrity fundamentals, Time Domain Reflectometry (TDR) is the gold standard for bench verification.
The TDR Before-and-After Test Sequence
TDR works by sending a fast-rising step edge down the trace and measuring the reflections over time. It effectively plots impedance versus distance.
- Setup: Connect a high-bandwidth active probe or a dedicated TDR module (like the Tektronix TDR80E04) to the SMA launch connector or directly to the driver pin via a ground-signal probe tip.
- Baseline (Before Fix): Trigger the TDR step. If you see the impedance curve spike above 50Ω, you have an inductive discontinuity (likely a via without a return via). If it dips below 50Ω, you have a capacitive discontinuity (likely a trace widening over a plane gap or a large SMD pad).
- Apply Fix: Add your series termination resistor or stitch a ground via next to your signal via to provide a continuous return path.
- Verify (After Fix): Re-trigger the TDR. The impedance curve should now remain a flat, monotonic line at 50Ω (±10%) from the driver to the receiver. On a standard oscilloscope eye diagram, this translates to an open, clean "eye" with minimal crossing-point jitter.
For a deeper dive into interpreting TDR waveforms and S-parameters, the Texas Instruments Signal Integrity Training Series provides excellent visual breakdowns of how specific PCB geometries reflect on a scope.
Shielding and Ground-Termination Rules
When routing off-board via cables, or using copper pours for shield cans on-board, shielding is only as effective as its ground termination. A common, fatal mistake is treating a shield as a simple physical barrier without managing the return currents.
The Golden Rule of Shielding: Never use a "pigtail" ground wire to terminate a cable shield. A pigtail introduces high inductance, effectively turning your shield into a resonant antenna above a few megahertz.
- For PCB Shield Cans: The copper pour must be tied to the internal ground plane using a continuous fence of vias. Space the vias at least 1/20th of the wavelength of your highest harmonic frequency apart (typically < 2mm spacing for 2.4 GHz Wi-Fi).
- For Coaxial / Shielded Cables: Terminate the shield 360-degrees to the chassis or PCB ground plane using a proper backshell or shield-clamp connector. This ensures the high-frequency return currents flow smoothly from the cable shield onto the ground plane without choking through an inductive wire.
Understanding what is an impedance in the context of the entire signal loop—from the driver silicon, through the PCB dielectric, and back via the ground plane—is what separates functional prototypes from manufacturable, EMC-compliant products. Control your geometry, terminate your mismatches, and verify with TDR.
