A voltage follower circuit (also known as a unity-gain buffer) outputs exactly the voltage applied to its non-inverting input. It provides a voltage gain of exactly 1 (0 dB), but its true purpose is impedance transformation: it presents a near-infinite input impedance to the source while providing a very low output impedance to drive heavy loads. If you need to read a high-impedance piezo sensor with a microcontroller ADC, or drive a 50-ohm coaxial cable from a weak signal source, this is the topology you build.
The Topology: Node Labels and the Alternative Contrast
The standard voltage follower uses an operational amplifier (op-amp) in a non-inverting configuration with 100% negative feedback. Here is the node mapping:
- Node 1 (V_in): The input signal connects to the non-inverting input (+).
- Node 2 (V_fb): The inverting input (-) is tied directly to the output node.
- Node 3 (V_out): The output pin, which feeds back to Node 2 and drives the load.
Because the op-amp’s open-loop gain is massive (typically 100 dB to 120 dB), the internal error amplifier drives the output until the voltage at the inverting input perfectly matches the non-inverting input. Thus, V_out = V_in.
Why This Topology Over the Alternatives?
You might wonder why you cannot just use a bare wire or a discrete BJT emitter follower. A bare wire fails because of loading effects; if your source has a 100 kΩ output impedance and your load is 10 kΩ, a direct wire creates a voltage divider that destroys your signal amplitude. A BJT emitter follower solves the impedance mismatch but introduces a base-emitter voltage drop (V_be) of roughly 0.65V, requires biasing resistors, and has an input impedance limited to β × R_load. The op-amp voltage follower eliminates the V_be drop, requires no biasing network for DC signals, and offers input impedances in the teraohm range for CMOS/FET input stages.
Behavior Matrix: Parameter Changes and Circuit Response
Understanding how the circuit reacts when you alter a single element is critical for debugging. The table below maps specific changes to their physical outcomes.
| Element Changed | Action | Circuit Response | Limiting Factor |
|---|---|---|---|
| Input Voltage (V_in) | Increase DC level | V_out tracks V_in perfectly | Op-amp common-mode input range and output swing limits (rail headroom) |
| Load Resistance | Decrease (heavier load) | V_out remains stable | Op-amp maximum short-circuit current (typically 20mA to 40mA) |
| Feedback Path | Add 10 kΩ resistor to ground | Circuit becomes a non-inverting amplifier (Gain = 2) | Resistor thermal noise and op-amp gain-bandwidth product |
| Input Source Impedance | Increase to 10 MΩ | V_out tracks, but DC offset may appear | Op-amp input bias current creating a voltage drop across the source |
Failure Modes at the Extremes: Shorts and Opens
When designing for the real world, you must account for fault conditions. Here is what breaks when the circuit is pushed to its physical extremes.
If the output node is accidentally shorted to 0V, the op-amp attempts to source infinite current to maintain V_out = V_in. Modern op-amps feature internal short-circuit protection. The output stage will current-limit (usually around 25mA to 40mA). The chip will not immediately explode, but the silicon die will dissipate significant heat (P = V_supply × I_limit). Prolonged shorting will trigger thermal shutdown or permanently degrade the output transistors.
If the wire connecting V_out to the inverting input breaks (open circuit), the negative feedback loop is destroyed. The op-amp reverts to its open-loop gain (e.g., 120 dB). Even a microvolt of difference between the inputs, caused by input offset voltage or electromagnetic interference, will be amplified by a million. The output will instantly slam into the positive or negative supply rail. The circuit is now acting as a high-gain comparator, not a buffer.
Decision Tree: Choosing the Right Op-Amp
Not all op-amps are suited for unity-gain buffering. Some are not "unity-gain stable" and will oscillate when configured with 100% feedback due to insufficient phase margin. Use this decision path to select your silicon.
| If Your Application Requires... | Then You Need These Specs... | Concrete Part Number |
|---|---|---|
| 5V single supply, buffering high-Z piezo or pH sensors | Rail-to-rail I/O, CMOS input (pA bias current), unity-gain stable | OPA340 (Texas Instruments) |
| +/- 15V dual supply, driving audio lines or low-noise analog stages | JFET input, low voltage noise, high slew rate | TL072 (Texas Instruments) |
| 3.3V battery-powered IoT node, ultra-low power consumption | Quiescent current < 100µA, SC70 package | MCP6001 (Microchip) |
| Driving heavy capacitive loads (long coax, ADC sample caps) | High output current, robust phase margin | OPA350 (Texas Instruments) |
Default Recommendation: If you are building a general-purpose 5V bench buffer and do not have a specific constraint, buy the OPA340. It is unity-gain stable, rail-to-rail, handles single-supply 5V flawlessly, and costs roughly $2.50 in single quantities.
Design Walkthrough: Building a 5V Sensor Buffer
Let’s design a buffer to isolate a 10 kΩ thermistor voltage divider from a microcontroller’s SAR ADC, which has a dynamic input impedance that drops to a few kilo-ohms during the sampling phase. We will use the OPA340.
Component Selection and Values
- U1: OPA340NA (SOT-23-5 package).
- C1 (Decoupling): 100 nF X7R ceramic capacitor. Placed physically within 2 mm of the VCC and GND pins to suppress high-frequency supply bounce.
- R_iso (Output Isolation): 100 Ω resistor. This is the most critical component in the design. Microcontroller ADCs use internal sample-and-hold capacitors (typically 10pF to 20pF). When the ADC samples, it switches this capacitor onto the input pin, creating a sudden capacitive load. Driving a capacitive load directly with an op-amp introduces a pole in the feedback loop, destroying phase margin and causing high-frequency ringing. The 100 Ω resistor isolates the op-amp output from the ADC capacitance.
- R_pull: 1 MΩ resistor from non-inverting input to GND. Provides a DC return path for the input bias current if the source is AC-coupled or high-impedance.
For deeper reading on why capacitive loads cause op-amp instability and how R_iso fixes it, refer to the Analog Devices guide on avoiding op-amp instabilities.
Step-by-Step Breadboard Testing and Verification
Do not just wire it up and assume it works. Follow this verification sequence to prove the buffer is operating within its linear region.
- Power Off & Continuity Check: With the breadboard unpowered, use your multimeter in continuity mode. Verify that the VCC pin is not shorted to GND. Verify that the inverting input (Pin 4 on SOT-23-5) has exactly 0 Ω resistance to the output side of the 100 Ω isolation resistor.
- Quiescent Current Measurement: Power the board with 5.00V. Break the VCC connection and insert your multimeter in series (current mode). The OPA340 should draw roughly 0.25 mA. If you read > 5 mA, you have a wiring fault or a damaged chip.
- DC Offset Verification: Tie the non-inverting input directly to GND. Measure the voltage at the output node (after the 100 Ω resistor) with a 4.5-digit DMM. You should read between -1 mV and +1 mV. If you read > 10 mV, your breadboard has leakage currents or the chip has a severe offset fault.
- Load Regulation Test: Apply a precise 2.500V DC to the input. Measure the output voltage with no load. Then, connect a 100 Ω load resistor from the output to GND. The output voltage should not drop by more than 5 mV. A larger drop indicates the op-amp is struggling with output stage saturation or your power supply is sagging.
- AC Slew Rate & Ringing Check: Connect a function generator to the input and set it to a 10 kHz square wave, 2Vpp. Probe the input (Channel 1) and the output (Channel 2) with an oscilloscope. The output square wave should have clean, sharp edges. If you see high-frequency ringing (oscillations) on the rising and falling edges, your 100 Ω isolation resistor is too low for the specific capacitive load you are driving; increase it to 220 Ω.
By strictly following this topology, respecting the phase-margin requirements of capacitive loads, and verifying the extreme failure modes, your voltage follower circuit will act as an invisible, perfect conduit for your analog signals.
