A voltage divider with capacitor (capacitive voltage divider) uses two series capacitors to divide AC signals without dissipating real power. Unlike resistive dividers, the voltage drop across a capacitor is inversely proportional to its capacitance. The governing formula is V_out = V_in × [C1 / (C1 + C2)], where C1 is the top capacitor (connected to the source) and C2 is the bottom capacitor (connected to ground). This topology is essential for high-voltage AC measurement, transformerless power supplies, and AC signal conditioning where heat dissipation must be minimized.
Topology and the Inverse Ratio Rule
The standard capacitive divider consists of three primary nodes:
- Node A (V_in): The AC source input, connected to the top of C1.
- Node B (V_out): The junction between C1 and C2, where the divided signal is extracted.
- Node C (GND): The bottom of C2, tied to the system ground or neutral.
The most common trap for hobbyists transitioning from DC resistive dividers is the inverse ratio. Because capacitive reactance (X_c = 1 / (2πfC)) decreases as capacitance increases, the larger capacitor drops the smaller voltage. If you want a 10:1 step-down ratio, C2 must be roughly 9 times larger than C1.
Parameter Behavior Matrix
Understanding how component drift or frequency shifts affect Node B is critical for stable AC design. The table below maps parameter changes to their direct effect on V_out.
| Parameter Changed | Direction of Change | Effect on V_out (Node B) | Physical Reason |
|---|---|---|---|
| C1 (Top Capacitor) | Increases | Increases | X_c1 drops, shifting more voltage across C2 |
| C2 (Bottom Capacitor) | Increases | Decreases | X_c2 drops, shorting more of the signal to ground |
| AC Frequency (f) | Increases | No Change (Ideal) | Both X_c1 and X_c2 drop proportionally; ratio holds |
| Bleed Resistor (R_bleed) | Decreases | Decreases | Forms a resistive divider with C1's impedance at low frequencies |
| Load Impedance at Node B | Decreases (Heavy Load) | Decreases drastically | Load parallels C2, altering the effective bottom capacitance |
Design Walkthrough: 12V AC to 1.2V AC Signal Conditioning
Let us design a divider to step down a 12VRMS (60Hz) doorbell transformer signal to a safe ~1.1VRMS peak for a 3.3V microcontroller ADC. We need a division ratio of roughly 0.09.
1. Selecting the Capacitors
Using the formula Ratio = C1 / (C1 + C2), we set the target to 0.0909 (a 10:11 ratio).
- Choose a standard value for C1: 100nF (0.1µF).
- Solve for C2:
0.0909 = 100n / (100n + C2)→ C2 ≈ 900nF. - Select the closest standard E12 value for C2: 1µF (1000nF).
Recalculated Ratio: 100 / (100 + 1000) = 0.0909.
Expected V_out: 12V × 0.0909 = 1.09VRMS. The peak voltage will be 1.09 × 1.414 = 1.54V, which sits comfortably inside the 0-3.3V ADC window.
2. Component Specifications
Do not use cheap Y5V or X7R ceramics for C1 and C2 in AC signal paths; they exhibit severe voltage coefficient (capacitance drops as voltage rises) and microphonic noise.
- C1 & C2: Use C0G/NP0 multilayer ceramic capacitors (MLCC) or metallized polypropylene film capacitors (e.g., WIMA MKS or EPCOS B3252x series). Film caps are physically larger but offer near-zero dielectric absorption.
- Voltage Rating: Minimum 50VDC / 25VAC for a 12V source. If adapting this for 120V mains, C1 must be an X2-rated safety capacitor (e.g., 100nF 275VAC X2) to survive line transients.
3. The Bleed Resistor
Add a 1MΩ, 1/4W metal film resistor in parallel with C2. This creates an RC time constant of 1 second (1MΩ × 1µF), safely discharging C2 when power is removed and providing a DC return path for the oscilloscope probe or ADC sampling capacitor.
Capacitive vs. Resistive Dividers
Why choose a voltage divider with capacitor over a standard two-resistor network? The decision hinges on power dissipation, DC isolation, and frequency stability.
| Criterion | Capacitive Divider (C1 + C2) | Resistive Divider (R1 + R2) |
|---|---|---|
| Real Power Dissipation | Near zero (reactive only) | High (dissipates heat, I²R losses) |
| DC Blocking | Blocks DC naturally (high-pass) | Passes DC and AC equally |
| Frequency Response | Flat for AC, but phase-shifted | Flat for both AC and DC (ignoring parasitics) |
| High Voltage Suitability | Excellent (using X/Y safety caps) | Poor (requires massive series resistor chains) |
| Output Impedance | High, frequency-dependent | Fixed, predictable DC resistance |
Choose Capacitive when: You are measuring high-voltage AC (like mains), need to block a DC offset from an AC signal, or must minimize heat in a sealed enclosure.
Choose Resistive when: You need to divide DC voltages, require a precise frequency-independent phase response, or are driving a low-impedance load directly.
Failure Modes and Extreme Edge Cases
When designing for production or harsh environments, you must account for what happens when components fail or operate at their physical extremes. According to electronics-tutorials.ws, capacitive reactance approaches infinity at DC, which fundamentally alters failure diagnostics.
Short and Open Circuit Matrix
| Failure Event | Result at Node B (V_out) | System Consequence |
|---|---|---|
| C1 Shorts | V_out = V_in (Full 12V AC) | Catastrophic: Overvoltage destroys downstream ADC/microcontroller. |
| C1 Opens | V_out = 0V | Safe failure: Signal loss, system reads zero. |
| C2 Shorts | V_out = 0V | Safe failure: Signal grounded, blows upstream fuse if source is low-impedance. |
| C2 Opens | Node B floats | Erratic readings; Node B charges to peak AC voltage via stray capacitance. |
The Dielectric Absorption Edge Case
If you use high-K ceramics (X7R, Y5V) instead of C0G or film, you will encounter dielectric absorption (DA). DA causes the capacitor to 'remember' previous voltage states and slowly release them. In a capacitive divider, this manifests as a slow, creeping DC offset at Node B that takes minutes to settle after power-on. For precision AC measurement, DA ruins accuracy. Always specify C0G/NP0 or film dielectrics for signal-path capacitors.
Step-by-Step Breadboard Verification
Do not trust the math until you have verified it on the bench. Capacitors have wide tolerances (often ±10% to ±20%), and breadboard parasitic capacitance can skew high-frequency results. Follow this procedure to validate your 12V AC divider.
- Prepare the Source: Set a function generator to output a 12Vpp (peak-to-peak) sine wave at 1kHz. (We use 1kHz instead of 60Hz for bench testing to make oscilloscope triggering easier and to minimize 60Hz mains hum pickup on the breadboard).
- Insert Components: Place the 100nF C0G capacitor (C1) and 1µF C0G capacitor (C2) in series on the breadboard. Insert the 1MΩ bleed resistor in parallel with C2.
- Compensate the Probe: Connect your oscilloscope probe to the built-in square wave calibration terminal and adjust the probe's compensation trimmer until the square wave edges are perfectly flat. An uncompensated probe will introduce its own capacitance (typically 10-15pF) in parallel with C2, skewing your high-frequency readings.
- Measure V_in: Probe Node A (across the function generator output). Verify it reads exactly 12Vpp.
- Measure V_out: Move the probe to Node B. You should read approximately 1.09Vpp. If the reading is slightly high (e.g., 1.15V), your C2 is likely sitting at the -10% tolerance bound (0.9µF actual).
- Check Phase Shift: Connect Channel 1 to Node A and Channel 2 to Node B. Trigger on Ch1. Because the load is purely reactive (ignoring the 1MΩ bleed), you will observe a phase shift between the two waveforms. This is normal and must be accounted for in software if you are calculating real power (Watts) in an energy monitoring application.
By understanding the inverse ratio, selecting the correct dielectric, and protecting against short-circuit failures, the voltage divider with capacitor becomes a highly reliable, zero-heat method for AC signal conditioning.
