Designing Capacitance in a Circuit: Two-Stage RC Filter for ESP32 ADCs

When integrating capacitance in a circuit for microcontroller analog-to-digital converter (ADC) inputs, a single bypass capacitor is rarely sufficient. The ESP32’s internal sample-and-hold (S/H) circuitry draws sharp, nanosecond-scale current spikes during sampling. If your external source impedance is too high, or your filtering is too weak, these spikes cause voltage droop, resulting in noisy, non-linear ADC readings. The direct, default solution for general sensor conditioning is a two-stage RC low-pass filter utilizing a 1kΩ/100nF primary stage and a 100Ω/10nF isolation stage. This topology provides both anti-aliasing and a local charge reservoir, guaranteeing clean data without starving the ADC.

The Two-Stage RC Topology for ADC Signal Conditioning

A single-stage RC filter (one resistor, one capacitor) rolls off high-frequency noise at -20dB/decade. While this handles basic smoothing, it fails to isolate the ADC pin from high-frequency digital switching noise on the PCB, nor does it provide a sufficiently stiff local charge bucket to absorb the S/H capacitor kickback. The two-stage topology solves this by splitting the resistance and capacitance across two distinct nodes.

Topology and Node Labels:

• Node A ($V_{in}$): The raw sensor output or noisy signal source.
• R1 (Series Resistor 1): Connects Node A to Node B. Sets the primary noise filter cutoff alongside C1.
• Node B ($V_{mid}$): The intermediate filtered node. Handles the bulk of the AC noise attenuation.
• C1 (Shunt Capacitor 1): Connects Node B to Ground (GND). The primary anti-aliasing capacitor.
• R2 (Series Resistor 2): Connects Node B to Node C. Acts as an isolation resistor to prevent C2 from resonating with the source and limits kickback current.
• Node C ($V_{out}$): The final output, wired directly to the microcontroller ADC GPIO.
• C2 (Shunt Capacitor 2): Connects Node C to GND. Acts as a high-frequency shunt and a localized charge reservoir to instantly satisfy the ADC’s S/H sampling demands.

Why this over a single-stage alternative? If you use a single 1.1kΩ resistor and a 110nF capacitor, the ADC’s internal sampling switch closing will pull charge directly through the 1.1kΩ resistor. This causes a momentary voltage drop at the ADC pin that hasn't settled by the end of the sampling window. By splitting the network, C2 (located physically adjacent to the ADC pin) supplies the instantaneous transient charge, while R2 isolates C2 from the rest of the circuit, allowing C1 to recharge C2 smoothly between samples.

Behavior Matrix and Failure-Mode Contrast

Understanding how capacitance in a circuit reacts to extremes is critical for debugging. A multimeter reading of 0V or floating noise usually traces back to one of these specific failure modes.

Design Walkthrough: Sizing for an ESP32 ADC

Let’s pick real component values for a slow-moving analog sensor, like an NTC thermistor or a potentiometer, feeding an ESP32 ADC input. The Espressif hardware design guidelines mandate that the source impedance driving the ADC be kept as low as possible—ideally under 10kΩ, and practically under 1kΩ—to ensure the internal 10pF S/H capacitor charges fully within the ~1µs sampling window.

Stage 1: The Primary Filter (Node A to Node B)

• R1: 1kΩ (0805 package, 1% tolerance, thin film).
• C1: 100nF (0.1µF).
• Cutoff Frequency ($f_c$): $f_c = \frac{1}{2\pi R_1 C_1} = \frac{1}{2\pi \times 1000 \times 100 \times 10^{-9}} \approx 1.59 \text{ kHz}$.
• Dielectric Choice: Use X7R here. X7R ceramics exhibit voltage coefficient and microphonic noise (piezoelectric effect), but at Node B, the signal is already heavily attenuated for high frequencies, and the physical vibration-induced noise won't significantly impact a slow DC sensor reading.

Stage 2: The Isolation and Charge Bucket (Node B to Node C)

• R2: 100Ω (0805 package, 1% tolerance).
• C2: 10nF (0.01µF).
• Cutoff Frequency ($f_c$): $f_c = \frac{1}{2\pi R_2 C_2} = \frac{1}{2\pi \times 100 \times 10 \times 10^{-9}} \approx 159 \text{ kHz}$.
• Dielectric Choice: Use C0G (NP0). This is non-negotiable for the final node. C0G dielectrics have zero voltage coefficient and negligible microphonic noise. Because C2 sits directly on the ADC pin, any piezoelectric noise generated by board flexure would be sampled directly as a false voltage reading. TI’s ADC circuit design resources consistently highlight the importance of low-distortion dielectrics at the final sampling node.

Breadboard Verification Steps

Before committing this topology to a printed circuit board, validate it on a solderless breadboard. Parasitic capacitance on a breadboard (typically 2pF–5pF per contact) won't ruin a 1.5kHz filter, but poor wiring will.

1. De-energize and Wire the Source: Connect your sensor output (or a function generator for testing) to the breadboard rail representing Node A. Connect the ESP32 GND to the breadboard ground rail.
2. Place Stage 1: Insert R1 (1kΩ) from Node A to a new row (Node B). Place C1 (100nF X7R) from Node B to the GND rail. Keep C1's leads as short as physically possible.
3. Place Stage 2: Insert R2 (100Ω) from Node B to another new row (Node C). Place C2 (10nF C0G) from Node C to the GND rail.
4. DC Verification (Multimeter): Power the circuit. Set your DMM to DC voltage. Measure Node A, Node B, and Node C. For a DC source, all three nodes should read the exact same voltage (within the DMM's mV resolution). If Node C is lower than Node A, you have a short to ground or a massive DC load on the ADC pin.
5. AC Rejection Test (Oscilloscope): Inject a 1V peak-to-peak, 10kHz sine wave superimposed on a 1.5V DC offset at Node A. Probe Node C. You should see a flat 1.5V DC line. The 10kHz signal is well above the 1.59kHz cutoff of Stage 1 and should be attenuated by at least -30dB. If you still see ripple, check for ground loops or breadboard parasitic coupling.
6. ADC Sampling Test: Wire Node C to the ESP32 GPIO. Run a continuous sampling loop in your firmware. If the standard deviation of your readings (with a static DC input) is greater than 3-4 LSBs, your C2 capacitor is likely the wrong dielectric (X7R instead of C0G) or is missing entirely.

Decision Tree: Selecting Your Filter Topology

While the 1kΩ/100nF + 100Ω/10nF network is the gold standard for general-purpose ESP32 sensor interfacing, different signal bandwidths require scaling the components. Use this decision matrix to lock in your final BOM.

The Final Pick: If you are building a mixed-signal IoT dashboard or a general-purpose sensor node and don't want to recalculate cutoff frequencies for every peripheral, standardize your BOM on the 1kΩ/100nF + 100Ω/10nF topology. Order the Murata GRM21BR71H104KA88 for your bulk decoupling and primary filtering, and the Murata GCM2195C1H103JA16 for your ADC charge buckets. This specific combination provides a robust, low-impedance interface that satisfies the ESP32’s demanding ADC architecture while effectively rejecting the high-frequency switching noise generated by the chip's own internal DC-DC converters and WiFi radios.