When analyzing a DC or AC circuit, each of two equal capacitors in series has exactly half the total applied voltage across its terminals ($V/2$), while the equivalent capacitance of the pair drops to half the value of a single capacitor ($C/2$). This assumes ideal components or perfectly matched leakage currents. In real-world applications, achieving this perfect 50/50 split requires deliberate circuit design to counteract manufacturing tolerances and dielectric absorption.
To visualize the topology, define three nodes: Node A (Source/V+), Node B (the midpoint junction between the two components), and Node C (Ground/Return). Capacitor $C_1$ bridges Node A and Node B. Capacitor $C_2$ bridges Node B and Node C. The total voltage $V_{AC}$ is applied across the outer nodes, while the voltage across each individual component is measured from the outer node to the shared Node B.
Behavior Matrix: Component Changes and Failure Extremes
Why choose a series topology over a parallel alternative? Parallel configurations sum capacitance ($C_{total} = C_1 + C_2$) but maintain the lowest voltage rating of the group. Series configurations halve the capacitance but double the voltage withstand rating. You use series topologies when your bus voltage exceeds the maximum rated voltage of available, cost-effective capacitors.
However, the midpoint voltage (Node B) is highly sensitive to component asymmetry. The table below details how the circuit behaves when one element deviates from the ideal.
| Element Deviation | Effect on Node B (Midpoint Voltage) | Effect on Total $C_{eq}$ | Real-World Consequence |
|---|---|---|---|
| $C_1$ value drifts +20% | Node B voltage drops below $V/2$ | $C_{eq}$ increases slightly | $C_2$ absorbs excess voltage; risks overvoltage failure if near rated limit. |
| $C_1$ ESR increases | No DC shift; AC ripple shifts to $C_1$ | Minimal change | $C_1$ runs hotter under AC ripple current, accelerating dry-out in electrolytics. |
| $C_1$ leakage current spikes | Node B voltage shifts toward Node A | No change | $C_2$ is forced to block nearly the full bus voltage, leading to cascading thermal runaway. |
Failure Extremes: What Breaks at the Limits?
Understanding failure modes is critical for high-voltage power supply design. If $C_1$ shorts, Node A and Node B become equipotential. The full bus voltage is instantly applied across $C_2$. Unless $C_2$ is rated for the full bus voltage (which it isn't, since we chose series to handle high voltage), $C_2$ will likely suffer a catastrophic dielectric breakdown, shorting the entire rail and tripping the upstream breaker or destroying the switching MOSFETs.
If $C_1$ opens (e.g., a fractured internal lead or a blown internal fuse), the series path is broken. $C_{eq}$ drops to zero. In a DC blocking application, signal transmission stops entirely. In a snubber or filter network, the circuit loses its high-frequency bypass path, resulting in massive voltage ringing on the primary switch node.
Design Walkthrough: Building a 400V DC Bus Filter
Let us design a practical filter for a 350V DC bus (nominal). We need an equivalent capacitance of 5µF rated for at least 400V. High-voltage 400V electrolytic capacitors are expensive and have long lead times. Instead, we will use two standard, readily available 10µF 250V aluminum electrolytic capacitors (e.g., Panasonic EEUEE2E100 or similar 105°C rated parts) in series.
Step 1: Verify the Math
$C_{eq} = \frac{10\mu F \times 10\mu F}{10\mu F + 10\mu F} = 5\mu F$.
Voltage rating = $250V + 250V = 500V$. This provides a safe 30% derating margin above our 350V bus.
Step 2: Calculate Balancing Resistors
Electrolytic capacitors have significant, and often mismatched, leakage currents. The datasheet specifies a maximum leakage of $I = 0.01 \times C \times V$, which equals $25\mu A$ for our 10µF 250V parts. If $C_1$ leaks $5\mu A$ and $C_2$ leaks $25\mu A$, the midpoint voltage will drift dangerously. We must add parallel bleeder/balancing resistors ($R_1$ and $R_2$) to swamp out this mismatch.
The current through the balancing resistors should be at least 10 to 50 times the maximum expected leakage current. Let us target a bleeder current of 1mA.
$R = \frac{V_{half}}{I_{bleeder}} = \frac{175V}{0.001A} = 175k\Omega$.
We will select standard 180kΩ, 1/2W metal film resistors (1% tolerance) to place in parallel with each capacitor.
Step 3: Verify Power Dissipation
$P = \frac{V^2}{R} = \frac{175^2}{180,000} \approx 0.17W$. A 1/2W resistor provides a comfortable safety margin. Total quiescent power wasted by the balancer network is 0.34W, an acceptable trade-off for preventing a $15 catastrophic bus failure.
Breadboard Testing Protocol
Before soldering this network into a high-voltage PCB, validate the balancing behavior on a breadboard using a safe, low-voltage DC source. Never breadboard 350V DC.
- Prepare the Breadboard: Insert two 100µF 16V electrolytic capacitors ($C_1$, $C_2$) in series. Connect the anode of $C_1$ to the positive rail (Node A). Connect the cathode of $C_1$ to the anode of $C_2$ (Node B). Connect the cathode of $C_2$ to the ground rail (Node C).
- Add Balancers: Insert two 10kΩ resistors in parallel with $C_1$ and $C_2$ respectively. (Scaled down for 12V testing).
- Energize and Settle: Apply 12V DC from a bench power supply to Node A. Wait 60 seconds. Dielectric absorption and capacitor charging require time for the midpoint to stabilize.
- Measure Node B: Use a digital multimeter (DMM) to measure the voltage from Node B to Node C. It should read exactly 6.00V (±0.1V).
- Induce Asymmetry: Remove the 10kΩ resistor across $C_1$. Wait 30 seconds. Measure Node B again. You will observe the voltage drift as the natural leakage mismatch of the two electrolytics takes over, proving why the balancing resistors are mandatory in the final high-voltage design.
- De-energize and Discharge: Turn off the power supply. Use a 1kΩ resistor to short Node A to Node C, safely discharging the stored energy before removing components.
Frequently Asked Questions
Does each of two equal capacitors in series have the same charge?
Yes. In a series circuit, the same charging current flows through all components for the exact same duration. Since charge $Q = I \times t$, the accumulated charge on the plates of $C_1$ and $C_2$ must be identical. Because $Q = C \times V$, and both $C$ and $Q$ are equal, the voltage $V$ across each must also be equal. This fundamental physics rule holds true regardless of the physical size or dielectric material of the capacitors, provided they are in a strict series loop.
What happens when each of two equal capacitors in series has mismatched ESR?
Equivalent Series Resistance (ESR) mismatch does not affect the DC voltage division, which is governed by capacitance and leakage/parallel resistance. However, under AC ripple conditions, the AC voltage drop divides proportionally to the ESR. The capacitor with the higher ESR will dissipate more $I^2R$ heat. In high-ripple applications like switch-mode power supply output filters, this localized heating accelerates electrolyte evaporation in the hotter capacitor, eventually causing it to fail open and shifting the entire AC ripple burden to the surviving component.
Can I use this topology to create a non-polarized capacitor from polarized parts?
Yes, by wiring two polarized electrolytic capacitors in series "back-to-back" (either anode-to-anode or cathode-to-cathode). This is a common technique in audio crossover networks or AC coupling applications where non-polarized film capacitors of the required value would be physically massive. However, you must ensure the peak AC voltage plus any DC offset never exceeds the reverse voltage rating of the individual capacitors, and you should add high-value diodes in parallel with each capacitor to clamp reverse bias to a safe ~0.6V if the signal swings too hard.
