The Series Capacitor Topology: Node Labels and Core Math
Wiring two capacitors in series reduces the total equivalent capacitance but stacks their voltage ratings, making it a standard technique for high-voltage DC bus filtering or creating non-standard low-capacitance values. The direct answer for the equivalent capacitance ($C_{eq}$) of two capacitors ($C_1$ and $C_2$) in series is calculated using the product-over-sum formula: $C_{eq} = (C_1 \times C_2) / (C_1 + C_2)$. If both capacitors are identical, the total capacitance is exactly half of a single unit's value, while the voltage rating doubles.
To understand the circuit behavior, we must define the topology with specific node labels:
- Node A (Input/High): The positive terminal of $C_1$, connected to the high-voltage source.
- Node B (Midpoint): The junction where the negative terminal of $C_1$ meets the positive terminal of $C_2$.
- Node C (Return/Ground): The negative terminal of $C_2$, connected to the circuit common or ground.
Unlike resistors in series, voltage across capacitors divides inversely proportional to their capacitance. The voltage across $C_1$ is $V_{C1} = V_{total} \times (C_2 / (C_1 + C_2))$. If $C_1$ is smaller than $C_2$, it will absorb a disproportionately larger share of the total voltage. This inverse relationship is the most common trap for beginners designing series capacitor networks.
Behavior Matrix and Extreme Failure Modes
When designing with capacitors in series, you must account for component degradation and catastrophic failure. The following behavior table details what happens to the circuit when one element shifts from its nominal state.
| Component Event | Effect on Total Capacitance | Effect on Node B Voltage Distribution | System Result & Risk |
|---|---|---|---|
| $C_1$ degrades (drops 20%) | $C_{eq}$ drops slightly | Node B voltage rises; $C_1$ takes more voltage | Mild stress on $C_1$, accelerated aging |
| $C_1$ fails OPEN | $C_{eq}$ drops to 0 µF | Circuit broken; no DC path | Loss of filtering; system brownout or shutdown |
| $C_1$ fails SHORT | $C_{eq}$ becomes equal to $C_2$ | Node B pulls to Node A; $C_2$ takes 100% of $V_{total}$ | Cascade Failure: If $V_{total}$ exceeds $C_2$ rating, $C_2$ vents or explodes |
Design Walkthrough: Building a 310V DC Bus Filter
Let us design a bulk filter for a rectified 220VAC mains supply. The peak DC voltage is roughly 310V. We need at least 200µF of bulk capacitance, but our parts bin only contains 200V-rated aluminum electrolytic capacitors. A single 200V cap will instantly fail on a 310V bus. We will wire two capacitors in series to stack the voltage rating to 400V.
Selected Components:
- $C_1$ & $C_2$: 470µF, 200V Aluminum Electrolytic (e.g., Nichicon UHW2D471MHD or similar 105°C rated part).
- $R_1$ & $R_2$ (Balancing Resistors): 47kΩ, 1W Metal Film.
Step 1: Calculate Equivalent Capacitance
Using identical 470µF caps: $C_{eq} = (470 \times 470) / (470 + 470) = 235\mu F$. This satisfies our 200µF minimum requirement. The series voltage rating is $200V + 200V = 400V$, safely covering the 310V peak.
Step 2: Address Leakage Current Mismatch
According to Nichicon application guidelines, aluminum electrolytic capacitors have inherent DC leakage currents that vary wildly from part to part, even within the same manufacturing batch. If $C_1$ has higher leakage than $C_2$, it acts as a lower impedance path, pulling Node B voltage down. This forces $C_2$ to absorb 250V, exceeding its 200V rating and causing premature dielectric breakdown.
Step 3: Add Balancing (Bleeder) Resistors
To force equal voltage division, we place a high-value resistor in parallel with each capacitor. We choose 47kΩ resistors. The current through the resistors ($I = 310V / 94k\Omega \approx 3.3mA$) must be at least 3 to 5 times higher than the worst-case capacitor leakage current (typically 0.5mA to 1mA for this size). This ensures the resistors dominate the DC voltage division, locking Node B at exactly 155V (half of 310V).
How to Breadboard-Test and Verify the Series Pair
Before soldering these into a high-voltage PCB, verify the topology on the bench using low-voltage test equipment. Follow these numbered steps to validate the series pair:
- Discharge and DMM Check: Short the capacitors with a 100Ω power resistor to ensure they are fully discharged. Set your digital multimeter to capacitance mode. Probe Node A and Node C. You should read approximately 235µF (allowing for the standard -20% / +20% electrolytic tolerance).
- DC Bias Midpoint Verification: Connect a bench power supply set to 10V DC across Node A (positive) and Node C (negative). Wait 30 seconds for the capacitors to charge and the leakage currents to stabilize. Probe Node B with respect to Node C. With balancing resistors installed, you must read exactly 5.0V (±0.2V). If you read 6.5V or 3.5V, your resistors are too large to overcome the leakage mismatch.
- AC Impedance and ESR Check: If you have an LCR meter, measure the Equivalent Series Resistance (ESR) at 100kHz. For two identical caps in series, the total ESR is the sum of the individual ESR values ($ESR_{eq} = ESR_1 + ESR_2$). If a single cap measures 40mΩ, the series pair should measure roughly 80mΩ.
- RC Time Constant Scope Test: For a dynamic test, apply a 10Hz, 0-5V square wave from a function generator to Node A. Connect an oscilloscope probe to Node B. The waveform will show an exponential charge/discharge curve. Measure the time it takes to reach 63.2% of the peak voltage ($\tau = R_{load} \times C_{eq}$) to empirically confirm the series capacitance value under dynamic conditions.
Series vs. Parallel: When to Use Which Topology
Why choose to wire two capacitors in series rather than parallel? The decision comes down to whether your bottleneck is voltage headroom or bulk energy storage. The table below contrasts the two configurations.
| Criteria | Two Capacitors in Series | Two Capacitors in Parallel |
|---|---|---|
| Total Capacitance | Decreases (Halves if identical) | Increases (Doubles if identical) |
| Voltage Rating | Increases (Stacks) | Limited by the lowest rated cap |
| Primary Use Case | High-voltage DC buses, center-tapping, voltage division | Low-voltage high-current ripple filtering, bulk energy storage |
| Failure Mode Risk | High (Cascade failure if one shorts) | Low (Shorted cap blows fuse; open cap just reduces total C) |
| Required Extras | Balancing/bleeder resistors mandatory for electrolytics | None required (though small gate resistors used in high-frequency switching) |
Frequently Asked Questions
Do two identical capacitors in series halve the capacitance?
Yes. When you wire two identical capacitors in series, the equivalent capacitance is exactly half the value of one individual capacitor. For example, two 100µF capacitors in series yield 50µF. This happens because the effective distance between the outermost plates increases, reducing the overall ability to store charge for a given voltage.
Why do my series capacitors keep failing in a high-voltage circuit?
Premature failure in series capacitor banks is almost always caused by unequal voltage distribution due to mismatched DC leakage currents, combined with a lack of balancing resistors. When one capacitor leaks more than the other, the node voltage shifts, forcing the 'tighter' capacitor to absorb more than its rated voltage. Over time, this overvoltage degrades the dielectric oxide layer, leading to a short circuit and subsequent cascade failure of the entire bank. Always install parallel bleeder resistors to force equal voltage division.
Can I put two ceramic capacitors in series without balancing resistors?
Generally, yes. Class I and Class II ceramic capacitors (like C0G or X7R dielectrics) have exceptionally low and relatively symmetrical DC leakage currents compared to aluminum electrolytics. For low-to-medium voltage applications (under 50V), you can usually wire two ceramic capacitors in series without balancing resistors. However, in high-voltage applications (e.g., 1kV+ snubber circuits) or when using high-capacitance MLCCs where leakage becomes measurable, high-value grading resistors are still recommended to ensure predictable voltage sharing.
How does wiring two capacitors in series affect the equivalent series resistance (ESR)?
Wiring two capacitors in series adds their ESR values together ($ESR_{total} = ESR_1 + ESR_2$). This is a critical trade-off in power supply design. While you gain voltage headroom, you double the parasitic resistance, which increases $I^2R$ heating and reduces the capacitor bank's ability to filter high-frequency ripple current. If low ESR is critical, you must select individual capacitors with exceptionally low ESR specs to ensure the combined series ESR remains within acceptable thermal limits.
