A truth table maps every possible binary input combination to its resulting output. But on the workbench, a logic "1" isn't just a mathematical concept—it is a specific voltage threshold, and a "0" is a current-sinking capability. If you are designing a digital circuit, debugging a state machine, or interfacing an Arduino with raw logic ICs, you need more than abstract Boolean algebra. You need the exact part numbers, voltage thresholds, and timing realities that govern physical silicon.
Below is the definitive reference chart for standard logic gates, bridging the gap between theoretical truth tables and the physical 14-pin DIP integrated circuits you actually solder into your projects.
The Master Logic Gate Truth Table Reference
How to read this table: The Gate column identifies the logical function. The IEEE/IEC Symbol describes the standard schematic shape (per IEEE Std 91 / IEC 60617-12). The Truth Table lists the 2-input binary matrix (Inputs A,B → Output Y). Finally, the Standard DIP IC column provides the exact manufacturer part number for the most common through-hole packages. Bookmark the quick-jump rows below for the most frequently queried gates on the bench.
| Gate Type | IEEE Symbol Shape | Boolean Expression | Truth Table (A,B → Y) | Standard 14-Pin DIP IC |
|---|---|---|---|---|
| AND | D-shape, flat back | Y = A · B | 00→0, 01→0, 10→0, 11→1 | SN74HC08N / CD4081BE |
| OR | Curved back, pointed front | Y = A + B | 00→0, 01→1, 10→1, 11→1 | SN74HC32N / CD4071BE |
| NOT (Inverter) | Triangle with output bubble | Y = A' | 0→1, 1→0 (Single Input) | SN74HC04N / CD4069UB |
| NAND (Universal) | D-shape with output bubble | Y = (A · B)' | 00→1, 01→1, 10→1, 11→0 | SN74HC00N / CD4011BE |
| NOR (Universal) | Curved back with output bubble | Y = (A + B)' | 00→1, 01→0, 10→0, 11→0 | SN74HC02N / CD4001BE |
| XOR | OR shape with double curved back | Y = A ⊕ B | 00→0, 01→1, 10→1, 11→0 | SN74HC86N / CD4030BE |
| XNOR | XOR shape with output bubble | Y = (A ⊕ B)' | 00→1, 01→0, 10→0, 11→1 | SN74HC266N / CD4077BE |
Which Logic Family Voltage Column Applies to Your Circuit?
An ideal truth table treats inputs as pure 1s and 0s. In physical reality, a microcontroller outputting 3.3V might not register as a logic "1" on an older 5V TTL chip. To know which column of a logic datasheet applies to your installation, you must match the logic family's voltage thresholds to your system's VCC.
| Logic Family | VCC Range | VIH (Min High Input) | VIL (Max Low Input) | Max IOL (Sink Current) | Best Application |
|---|---|---|---|---|---|
| 74HC (CMOS) | 2.0V - 6.0V | 0.7 × VCC (3.5V @ 5V) | 0.3 × VCC (1.5V @ 5V) | ~4 mA per pin | General 5V/3.3V Arduino logic |
| 74LS (TTL) | 4.75V - 5.25V | 2.0V (Fixed) | 0.8V (Fixed) | ~8 mA per pin | Legacy 5V industrial repair |
| 74LVC (Low Voltage) | 1.65V - 3.6V | 2.0V (at 3.3V VCC) | 0.8V (at 3.3V VCC) | ~24 mA per pin | ESP32 / 3.3V Pi interfacing |
| 4000B (CMOS) | 3.0V - 15.0V | 0.7 × VCC | 0.3 × VCC | ~0.5 mA (at 5V) | 12V automotive / high voltage |
Choosing the right column: If you are wiring an ESP32 (3.3V logic) to drive a standard relay board, the 74LVC or 74HC (powered at 3.3V) columns apply. Do not use 74LS chips with 3.3V microcontrollers; the 74LS family requires a minimum of 2.0V to register a "High", and while 3.3V meets this, the noise margins are dangerously thin, and 74LS inputs source current that can backfeed into sensitive ESP32 GPIO pins.
What the Ideal Truth Table Cannot Tell You (Timing and Loading)
A printed truth table assumes instantaneous transitions and infinite drive strength. On the bench, parasitic effects modify these ideal behaviors. Understanding these limitations prevents the most common digital logic debugging nightmares.
How Loading and Fan-Out Derate the Ideal Output
In wire ampacity charts, derating rows reduce current capacity based on ambient temperature. In logic gate specifications, fan-out and capacitive loading derate the ideal truth table's timing and voltage margins. Every logic output has a maximum sink/source current (e.g., IOL = 4mA for 74HC). If you connect too many inputs to a single output (exceeding the fan-out limit, typically 10-20 standard CMOS inputs), the output voltage sags. A logic "0" might rise above the VIL maximum threshold of the receiving gate, causing a false "1" reading.
Furthermore, driving long wires or multiple inputs adds parasitic capacitance. This capacitance acts as a low-pass filter, derating the propagation delay (tpd). A gate that switches in 10ns on the datasheet might take 50ns to cross the logic threshold when heavily loaded, causing clock skew in high-speed state machines.
The Analog Transition Region and Metastability
What the binary truth table completely omits is the analog transition region. When an input voltage transitions from 0V to 5V, it must pass through the undefined linear region between VIL (max low) and VIH (min high). During this window, the internal PMOS and NMOS transistors are partially turned on simultaneously. This creates a direct path from VCC to GND, resulting in a spike of "shoot-through" current. If an input signal rises too slowly (like a raw RC circuit or a noisy mechanical switch), the gate will oscillate wildly in this undefined region, generating multiple false output pulses.
Finally, truth tables cannot model metastability. If you are using logic gates to build edge-triggered flip-flops or latches, the input data must be stable for a specific setup time before the clock edge, and a hold time after it. Violating these timing windows forces the output into a metastable state—a quantum-like limbo where the output voltage hovers between 0 and 1, or oscillates at high frequencies, until thermal noise eventually forces it to resolve to a valid logic level. Always use proper debouncing circuits or synchronizer flip-flops when bringing asynchronous real-world signals into a clocked logic domain.
