The truth tables of logic gates define two distinct but inseparable realities: the abstract Boolean relationship (1s and 0s) and the physical voltage thresholds that represent those states on a workbench. While a textbook shows you that a NAND gate outputs a 0 only when both inputs are 1, a bench engineer needs to know exactly what voltage constitutes a "1" for a 74HC00 versus a 74LS00. This reference bridges that gap, combining standard IEEE/IEC logic definitions with real-world electrical thresholds.
The Master Reference: Boolean and Electrical Truth Tables of Logic Gates
The table below merges the Boolean logic states with the electrical voltage thresholds for the two most common 5V logic families: 74LS (Low-power Schottky TTL) and 74HC (High-speed CMOS). Source standards: Boolean symbols follow IEEE Std 91-1984 / IEC 60617-12, while electrical thresholds are derived from the Texas Instruments Logic Guide (SDYA010) and standard manufacturer datasheets at $V_{CC}$ = 5.0V and $T_A$ = 25°C.
| Gate Type | Inputs (A, B) | Output (Y) | Logic Family | $V_{IL}$ (Max) | $V_{IH}$ (Min) | $V_{OL}$ (Max) | $V_{OH}$ (Min) |
|---|---|---|---|---|---|---|---|
| AND / NAND | 0, 0 / 0, 1 | 0 / 1 | 74LS (TTL) | 0.8V | 2.0V | 0.4V | 2.7V |
| 0, 0 / 0, 1 | 0 / 1 | 74HC (CMOS) | 1.5V | 3.5V | 0.33V | 4.4V | |
| OR / NOR | 0, 0 / 1, 0 | 0 / 1 | 74LS (TTL) | 0.8V | 2.0V | 0.4V | 2.7V |
| 0, 0 / 1, 0 | 0 / 1 | 74HC (CMOS) | 1.5V | 3.5V | 0.33V | 4.4V | |
| XOR / XNOR | 0, 0 / 1, 0 | 0 / 1 | 74LS (TTL) | 0.8V | 2.0V | 0.4V | 2.7V |
| 0, 0 / 1, 0 | 0 / 1 | 74HC (CMOS) | 1.5V | 3.5V | 0.33V | 4.4V | |
| NOT (Inverter) | 0 / 1 | 1 / 0 | 74LS (TTL) | 0.8V | 2.0V | 0.4V | 2.7V |
| 0 / 1 | 1 / 0 | 74HC (CMOS) | 1.5V | 3.5V | 0.33V | 4.4V |
Applying the Table: Logic Families, Fan-Out Derating, and Noise Margins
Knowing the Boolean logic is only half the battle. To design a reliable circuit, you must understand which columns apply to your specific installation and how real-world loading derates these baseline values.
Which Column Applies to Your Installation?
If you are designing the input side of a circuit (e.g., reading a sensor or a microcontroller GPIO), you must look at the $V_{IL}$ and $V_{IH}$ columns. Your signal source must swing below $V_{IL}$ to guarantee a low, and above $V_{IH}$ to guarantee a high. If you are designing the output side (e.g., driving an LED or feeding another chip), you must look at the $V_{OL}$ and $V_{OH}$ columns. These tell you the actual voltage the gate will supply to the next stage.
How Derating Rows Modify the Base Value
The values in the table assume a standard test load (typically a few milliamps). In practice, fan-out and capacitive loading derate these thresholds.
- DC Fan-Out Derating: If you connect a 74HC output to twenty 74LS inputs, the cumulative input leakage current ($I_{IL}$) of the LS chips will pull the HC output voltage down. The $V_{OH}$ of 4.4V might derate to 3.8V under heavy load.
- AC Capacitive Derating: Every logic input and PCB trace adds parasitic capacitance (typically 10pF to 15pF per load). As you increase the capacitive load, the rise and fall times of the output voltage degrade. At high switching frequencies, the voltage may never actually reach the $V_{OH}$ or $V_{OL}$ thresholds before the next clock edge arrives, effectively shrinking your noise margin to zero.
What the Table Cannot Tell You
A static truth table is blind to time. It cannot tell you the propagation delay ($t_{pd}$)—the nanoseconds it takes for a change at input A to appear at output Y. It also hides setup and hold times for flip-flops, and it completely ignores metastability (the chaotic analog state a gate enters when inputs change simultaneously). For timing-critical designs, you must consult the dynamic timing diagrams in the specific manufacturer datasheet, such as the TI SN74HC00 datasheet.
Quick-Jump Bookmark Guide for Common ICs
Use this quick reference to verify compatibility when mixing logic families on the bench. For deeper theory on logic families, consult the All About Circuits Digital Textbook.
- 74HC00 (Quad 2-Input NAND): CMOS. Excellent noise margins (0.9V DC noise margin at 5V). Requires all unused inputs to be tied to VCC or GND to prevent floating-input shoot-through current.
- 74LS08 (Quad 2-Input AND): TTL. Fast switching but poor high-level noise margin (only 0.7V). Inputs float high internally if left disconnected, but tying them down is still best practice.
- CD4011BE (Quad 2-Input NAND): 4000-series CMOS. Operates from 3V to 15V. Thresholds scale with $V_{CC}$ (typically $V_{IH}$ is 70% of $V_{CC}$, $V_{IL}$ is 30% of $V_{CC}$). Very slow propagation delay compared to 74-series.
- 74LVC00 (Low-Voltage CMOS): 3.3V logic family. 5V-tolerant inputs, making it the standard bridge chip for interfacing legacy 5V TTL outputs to modern 3.3V microcontrollers.
Frequently Asked Questions
Why do CMOS and TTL truth tables show different voltage thresholds?
TTL (Transistor-Transistor Logic) relies on bipolar junction transistors, which inherently drop voltage across base-emitter junctions, resulting in a weak logic high output (typically 2.7V to 3.4V). CMOS (Complementary Metal-Oxide-Semiconductor) uses MOSFETs that pull the output almost entirely to the supply rail, yielding a strong logic high (4.4V+ at a 5V supply). This fundamental semiconductor physics difference dictates why their $V_{IH}$ and $V_{OH}$ thresholds diverge so drastically.
What happens if an input voltage falls between V_IL and V_IH?
This region is known as the "forbidden zone" or indeterminate state. In TTL, the output may oscillate or settle unpredictably. In CMOS, lingering in this linear region turns on both the upper P-channel and lower N-channel MOSFETs simultaneously. This creates a direct short-circuit path from $V_{CC}$ to GND (shoot-through current), causing the IC to overheat, draw excessive current, and potentially fail. Never leave CMOS inputs floating; always use pull-up or pull-down resistors.
Can I mix 74HC and 74LS logic families in the same 5V circuit?
Yes, but with strict directional rules. A 74HC (CMOS) output can easily drive a 74LS (TTL) input because the HC's $V_{OH}$ (4.4V) is well above the LS's $V_{IH}$ (2.0V). However, driving a 74HC input directly from a 74LS output is risky: the LS chip's $V_{OH}$ (2.7V) falls short of the HC chip's required $V_{IH}$ (3.5V). To make LS-to-HC work reliably, you must add a pull-up resistor (typically 1kΩ to 4.7kΩ) to the LS output to boost the high voltage closer to 5V.
