The truth tables of all logic gates define the fundamental boolean relationships between digital inputs and outputs. However, on the workbench, a logical "1" or "0" is not an abstract concept—it is a specific voltage range dictated by the silicon family you are using. While textbooks present idealized boolean algebra, real-world digital design requires understanding how voltage thresholds, propagation delays, and fan-out loading modify those ideal tables in practice.
Below is the master reference chart for standard combinatorial logic, followed by the silicon-level data you actually need to wire these ICs without chasing phantom bugs.
The Master Truth Table Reference (IEEE/IEC Standard)
The following table covers the standard 2-input combinatorial gates, alongside the 1-input inverter. The logical definitions and standard graphic symbols for these gates are governed by IEEE Std 91-1984 and its international counterpart, IEC 60617-12.
| Input A | Input B | AND | OR | NAND | NOR | XOR | XNOR | NOT (A) |
|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 |
| 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 |
Bookmark this section for quick reference when debugging combinatorial logic networks or verifying FPGA lookup tables (LUTs).
Theory vs. Silicon: Which Logic Family Column Applies to Your Circuit
A truth table tells you that an input of "1" yields an output of "1". But which column applies to your specific installation? In physical wiring, the "1" and "0" columns are actually voltage thresholds, and those thresholds shift dramatically depending on the logic family etched into the silicon die.
If you are mixing logic families—for example, driving a 74LS00 (TTL) with a CD4011 (CMOS)—you must verify that the output voltage of the driving gate meets the input threshold requirements of the receiving gate. Here are the critical DC voltage specifications for the three most common hobbyist and industrial logic families at a standard 5.0V VCC rail.
| Parameter | 74LS (TTL) | 74HC (CMOS) | 4000B (CMOS) | Definition |
|---|---|---|---|---|
| VCC Range | 4.75V - 5.25V | 2.0V - 6.0V | 3.0V - 15.0V | Supply voltage tolerance |
| V_IH (Min) | 2.0V | 3.5V (at 5V VCC) | 3.5V (at 5V VCC) | Minimum voltage guaranteed as a logical "1" |
| V_IL (Max) | 0.8V | 1.5V (at 5V VCC) | 1.5V (at 5V VCC) | Maximum voltage guaranteed as a logical "0" |
| V_OH (Min) | 2.7V | 4.9V | 4.95V | Minimum output voltage when driving a "1" |
| V_OL (Max) | 0.5V | 0.1V | 0.05V | Maximum output voltage when driving a "0" |
Bench Reality: Notice the V_IH gap. A 74HC gate outputting a logical "1" at 4.9V easily drives a 74LS input (which only needs 2.0V). However, if you try to drive a 74HC input directly from a standard 5V microcontroller GPIO that sags to 3.0V under load, you fall below the 74HC's 3.5V V_IH threshold. The gate will read it as an undefined state, leading to erratic output. For 3.3V microcontroller environments, always use 74HCT series gates, which feature TTL-compatible input thresholds.
How Real-World Loading Derates the Ideal Truth Table
The master truth table assumes instantaneous transitions and infinite drive capability. In physical silicon, loading conditions act as "derating rows" that modify the base logical value by introducing time delays and voltage sag.
Propagation Delay (t_pd)
When inputs A and B change state, the output Y does not flip instantly. The propagation delay (t_pd) is the time it takes for the output to reach 50% of its final voltage after the input crosses the 50% threshold.
- 74LS00: Typical
t_pdis 9ns. - 74HC00: Typical
t_pdis 8ns at 5V, but jumps to 18ns at 2.0V. - CD4011: Typical
t_pdis 50ns at 5V, dropping to 25ns at 15V.
If you cascade ten 74HC gates in series, you accumulate ~80ns of delay. In high-speed clock circuits, this derating shifts the phase of your signal, potentially violating setup and hold times on downstream flip-flops.
Fan-Out and Current Loading
Fan-out defines how many gate inputs a single output can reliably drive. This is dictated by current, not just voltage.
- 74LS output: Can sink 8mA (logical 0) but only source 0.4mA (logical 1).
- 74HC output: Can source and sink roughly 25mA (absolute max, 4mA recommended for voltage spec compliance).
If you connect one 74LS00 output to twenty 74LS inputs, the cumulative input leakage current when pulling low will exceed the 8mA sink capability. The output voltage will rise above the 0.5V V_OL maximum, effectively derating your logical "0" into an undefined voltage. The truth table says "0", but your multimeter reads 1.2V.
What the Truth Table Cannot Tell You (Bench Gotchas)
Boolean algebra is perfect; silicon is not. Here are three critical failure modes that no truth table will warn you about, which I see constantly in hobbyist and student designs.
The truth table assumes inputs are strictly tied to VCC or GND. If you leave an input pin floating on a CMOS gate (like the 74HC or CD4000 series), the internal MOSFETs partially turn on. The gate will oscillate at high frequencies internally, drawing massive quiescent current (
I_DD). I have seen a single floating input on a CD4011BE cause the entire IC to overheat and draw 50mA, draining a 9V battery in hours. Always tie unused inputs to VCC or GND via a 10kΩ resistor.
2. Metastability and Race Conditions
If inputs A and B of an XOR gate transition from (0,0) to (1,1) simultaneously, the truth table says the output should remain "0". In reality, due to microscopic differences in internal transistor switching speeds, one input will cross the threshold nanoseconds before the other. The gate will briefly see (0,1) or (1,0), outputting a momentary "1" glitch before settling to "0". This is a race condition, and it will trigger edge-sensitive clocks if not filtered.
3. The Undefined Region
Look back at the voltage threshold table. For a 74HC gate at 5V, anything below 1.5V is a "0", and anything above 3.5V is a "1". What happens at 2.5V? The truth table has no row for 2.5V. In this undefined region, the output is unpredictable, and the gate's internal high-gain amplifiers may latch up or oscillate. Never intentionally design a circuit to operate in the linear region of a digital logic gate unless you are specifically using it as a poor-man's analog amplifier (which requires careful biasing and is generally discouraged).
For authoritative datasheet specifications and logic portfolio details, refer to the Texas Instruments Logic Portfolio or the NXP 74HC/HCT00 Datasheet. For foundational theory, the All About Circuits Digital Textbook remains an excellent, stable reference.
