When designing digital circuits or debugging a breadboard, understanding truth table symbols meaning is the baseline for predicting how binary inputs translate to physical voltage outputs. Truth table symbols are the standardized graphical, Boolean, and tabular representations of logic gates—defined primarily by IEEE Std 91 / ANSI Y32.14 and IEC 60617-12. They map every possible combination of input states (0 or 1) to a single deterministic output state, allowing engineers to synthesize complex sequential logic from basic combinational building blocks.
The Master Logic Symbol & Truth Table Reference
How to read this table: This reference aligns the traditional MIL-STD shapes you see on breadboard schematics with the rectangular IEEE/IEC symbols used in modern datasheets. The Boolean Expression column provides the algebraic formula, while the Truth Table column lists the exact binary output (Y) for a 2-input system (A, B). Crucially, the Logic Family column dictates the physical voltage requirements for your specific installation. Bookmark the quick-jump links below to navigate directly to the gate you are testing.
| Gate Name | Traditional Shape | IEEE/IEC Rectangular | Boolean Expression | Truth Table (A,B → Y) | Common 5V Part |
|---|---|---|---|---|---|
| Buffer | Triangle | 1 | Y = A | 0→0, 1→1 | SN74HC04N (Unused) |
| NOT (Inverter) | Triangle + Bubble | 1 (with bubble) | Y = A | 0→1, 1→0 | SN74HC04N |
| AND | D-Shape | & | Y = A · B | 00→0, 01→0, 10→0, 11→1 | SN74HC08N |
| NAND | D-Shape + Bubble | & (with bubble) | Y = A · B | 00→1, 01→1, 10→1, 11→0 | SN74HC00N |
| OR | Curved Arrowhead | ≥1 | Y = A + B | 00→0, 01→1, 10→1, 11→1 | SN74HC32N |
| NOR | Arrowhead + Bubble | ≥1 (with bubble) | Y = A + B | 00→1, 01→0, 10→0, 11→0 | SN74HC02N |
| XOR | Double-Curved | =1 | Y = A ⊕ B | 00→0, 01→1, 10→1, 11→0 | SN74HC86N |
| XNOR | Double-Curved + Bubble | =1 (with bubble) | Y = A ⊕ B | 00→1, 01→0, 10→0, 11→1 | CD4077BE |
Applying Logic Families: Voltage, Fan-Out, and Derating
In wire sizing, you look at temperature columns to find ampacity. In logic design, the Logic Family / Voltage column is what applies to your physical installation. A truth table assumes ideal 0s and 1s, but physical ICs require specific voltage thresholds to recognize those states. If you are building a 5V system, the Texas Instruments 74HC series (e.g., SN74HC00N) is your standard. If you are interfacing with older 12V automotive or industrial relays, you must step up to the CD4000 series (e.g., CD4011BE), which tolerates 3V to 15V.
A truth table assumes inputs are firmly tied to VCC (1) or GND (0). In physical CMOS ICs (74HC or CD4000), a floating (unconnected) input acts as an antenna, picking up electromagnetic noise. This causes the gate to oscillate rapidly, leading to massive internal current spikes that can overheat and destroy the IC. Always tie unused inputs to GND or VCC via a 10kΩ pull-down/pull-up resistor.
How Derating Modifies the Base Value
Just as wire ampacity derates when bundled in conduit, logic gate performance derates based on fan-out (capacitive load) and ambient temperature. The truth table gives you the logical result, but the datasheet gives you the timing. For a standard SN74HC00N NAND gate operating at 5V and 25°C with a minimal 15pF load, the propagation delay (tpd) is typically 8ns. However, if you wire that single output to ten other gate inputs (increasing the capacitive load to ~50pF) and the enclosure temperature rises to 85°C, the propagation delay derates to approximately 15ns. In high-speed clock circuits, this 7ns derating shift can cause setup-and-hold violations, pushing your flip-flops into metastability.
What the Truth Table Cannot Tell You
Truth tables are purely mathematical abstractions. When moving from simulation to the workbench, you must account for physical edge cases that the table completely hides:
- Propagation Delay (tpd): The output does not change instantaneously when inputs change. There is a nanosecond-scale lag. If inputs A and B of an XOR gate change states simultaneously but arrive 2ns apart due to trace length differences, the gate will output a brief, erroneous 'glitch' pulse before settling to the truth table's predicted state.
- Shoot-Through Current: During the microsecond an input transitions from 0 to 1, the internal PMOS and NMOS transistors inside a CMOS gate are briefly turned on at the same time. This creates a momentary short circuit from VCC to GND. While the truth table just shows a clean state change, your power supply must be decoupled with 100nF ceramic capacitors placed as close to the IC VCC pin as possible to absorb these transient current spikes.
- Metastability: If you feed an asynchronous, noisy mechanical switch bounce into a clocked flip-flop, the output may hover between 0 and 1 (e.g., 2.4V) for an extended period. The truth table has no row for '0.5'.
Frequently Asked Questions (FAQ)
What does the bubble or circle mean on a logic gate symbol?
The bubble (officially called an inversion indicator or negation circle) on either the input or output of a logic gate symbol means 'NOT'. It inverts the logic state. If a bubble is on the output of an AND gate, it becomes a NAND gate (output is LOW only when all inputs are HIGH). If a bubble is on an input, it means the gate triggers on a LOW signal rather than a HIGH signal. In Boolean algebra, this is represented by an overline or an apostrophe (e.g., A').
Why do IEEE/IEC rectangular symbols look different from traditional MIL-STD shapes?
Traditional shapes (D-shapes, arrowheads) are intuitive for simple 2-input gates but become impossible to draw for complex programmable logic or microcontrollers. The IEEE/IEC rectangular standard uses uniform boxes with internal text qualifiers (like '&' for AND, '≥1' for OR, or '=1' for XOR). This allows designers to map complex, multi-input, multi-output ICs on a single schematic sheet without drawing convoluted, unrecognizable shapes. You will see traditional shapes in hobbyist tutorials, but rectangular symbols on professional datasheets.
How do I read a truth table with 'Don't Care' (X) conditions?
In advanced logic synthesis (like designing a state machine), you will encounter 'X' or 'Don't Care' in a truth table. This means the output state does not matter for that specific input combination, usually because that input state is physically impossible or irrelevant to the system. When mapping these tables onto Karnaugh maps (K-maps) to simplify your Boolean algebra, you can treat the 'X' as either a 0 or a 1—whichever choice allows you to group the largest possible block of 1s, thereby minimizing the number of physical gates you need to wire on your breadboard.
What is the difference between an exclusive-OR (XOR) and an inclusive-OR (OR) in physical wiring?
An inclusive-OR (standard OR gate) outputs a 1 if any input is 1, including when both inputs are 1 (1+1=1). An exclusive-OR (XOR) outputs a 1 only if the inputs are different (1+0=1, but 1+1=0). In physical wiring, XOR gates are heavily used as parity generators and half-adders in arithmetic logic units (ALUs). If you are building a 2-way staircase light switch circuit where toggling either switch changes the light state, you are physically wiring an XOR logic function, even if you are using mechanical SPDT switches instead of silicon ICs.
