Truth tables define the mathematical logic of a circuit, but when you move from a textbook to a schematic capture tool like KiCad or Altium, you need standardized visual representations. Truth table symbols map binary input/output states to specific schematic shapes governed by two primary standards: IEEE Std 91-1984 (the US/Military standard using distinctive shapes) and IEC 60617-12 (the International standard using rectangular outlines).
How to Read the Truth Table Symbols Chart
The reference chart below bridges the gap between abstract Boolean algebra and physical schematic design. Before bookmarking the quick-jump rows, you need to understand how to apply these columns to your specific workflow.
If you are reading US-based datasheets (Texas Instruments, NXP US docs), working with legacy MIL-STD-806 designs, or taking a university digital logic course in North America, use the IEEE Shape column. If you are designing for international commercial compliance, submitting schematics to European manufacturers, or using modern EDA tools configured to IEC defaults, use the IEC Rectangular column.
How inversion and derating modify the base value: In power systems, derating rows reduce a wire's base ampacity. In digital logic, the equivalent concept is signal inversion (represented by a bubble) and temperature derating of logic thresholds. An inversion bubble on an input or output flips the truth table's 1s and 0s for that specific node—a NAND gate is simply an AND gate with an output bubble. Furthermore, when designing the physical circuit, you must check the IC's temperature derating tables; a base $V_{IH}$ (High-level input voltage) of 3.15V at 25°C may drop to 3.05V at 85°C, modifying the physical voltage required to satisfy the '1' in the truth table.
What the table cannot tell you: A truth table assumes ideal, instantaneous logic. It will not tell you the propagation delay ($t_{pd}$, typically 8ns to 15ns for standard 74HC series ICs), fan-out limits (how many inputs one output can drive before voltage droops), or power dissipation. You must cross-reference the truth table with the component's specific datasheet for timing and electrical characteristics.
The Master Truth Table & Schematic Symbol Reference
Use the quick-jump links below to find the specific gate you are troubleshooting, or scroll through the complete data table sourced from IEEE Std 91 and IEC 60617 standards.
| Gate Type | Boolean Expression | Truth Table (A, B → Y) | IEEE Symbol Shape (US/MIL) | IEC Symbol Shape (Intl) |
|---|---|---|---|---|
| AND | Y = A · B | 0,0→0 | 0,1→0 1,0→0 | 1,1→1 |
D-shaped flat back, curved front | Rectangle with '&' inside |
| OR | Y = A + B | 0,0→0 | 0,1→1 1,0→1 | 1,1→1 |
Curved back, pointed front | Rectangle with '≥1' inside |
| NOT (Inverter) | Y = A' | 0→1 | 1→0 | Triangle pointing right with output bubble | Rectangle with '1' and output bubble |
| NAND | Y = (A · B)' | 0,0→1 | 0,1→1 1,0→1 | 1,1→0 |
AND shape with output bubble | Rectangle with '&' and output bubble |
| NOR | Y = (A + B)' | 0,0→1 | 0,1→0 1,0→0 | 1,1→0 |
OR shape with output bubble | Rectangle with '≥1' and output bubble |
| XOR | Y = A ⊕ B | 0,0→0 | 0,1→1 1,0→1 | 1,1→0 |
OR shape with extra curved input line | Rectangle with '=1' inside |
| XNOR | Y = (A ⊕ B)' | 0,0→1 | 0,1→0 1,0→0 | 1,1→1 |
XOR shape with output bubble | Rectangle with '=1' and output bubble |
Real-World IC Mapping: From Symbols to Silicon
Knowing the truth table symbols is only half the battle; you have to buy the physical silicon to build the circuit. The most common logic families you will encounter on the bench are the 7400 series (TTL and CMOS) and the CD4000 series (CMOS).
If you need a quad 2-input AND gate, you will reach for a 74HC08 (CMOS, high-speed) or a 74LS08 (older TTL). The truth table for both is identical, but the physical electrical characteristics are vastly different. According to the Texas Instruments SN74HC08 datasheet, the 74HC08 operating from a 5V supply requires an input high voltage ($V_{IH}$) of at least 3.15V to register a '1' in the truth table. If you are interfacing this with a 3.3V ESP32 microcontroller, the ESP32's 3.3V HIGH output might fall dangerously close to the HC family's threshold, leading to logic errors. In that scenario, you should use a 74HCT08 (TTL-compatible thresholds) or a dedicated logic level shifter.
Frequently Asked Questions
What are the standard truth table symbols for a 3-input logic gate?
The truth table expands to eight rows (000 through 111), but the schematic symbol remains structurally identical to the 2-input version, simply with a third input line drawn on the back or side of the shape. In the IEC standard, a 3-input AND gate remains a rectangle with an '&' inside, while a 3-input OR gate changes its internal text from '≥1' to '≥1' (since 1 or more inputs must be high), but a 3-input majority gate would use specific IEC qualifiers. Always verify the pinout in the specific IC datasheet, as pin 1 is usually denoted by a notch or dot on the physical IC package.
How do I represent an active-low truth table symbol on a schematic?
Active-low signals are represented by adding an inversion bubble (a small circle) to the input or output pin of the logic symbol, accompanied by a text overline (e.g., RESET) or a slash prefix (/RESET) in the net label. In the truth table, an active-low input means that a physical '0' (0V) is interpreted as the logical 'TRUE' state for that specific condition. For example, a NAND gate can be drawn as an OR gate with active-low inputs (De Morgan's equivalent) to better reflect its actual function in a reset circuit.
Why do my KiCad truth table symbols look different from the IEEE shapes?
Modern EDA tools like KiCad and Altium Designer often default to the IEC 60617 rectangular standard for new library components because it is easier to parse programmatically and aligns with international commercial standards. If you prefer the traditional US/Military distinctive shapes (IEEE Std 91-1984), you can change this in your EDA tool's preferences or by downloading legacy symbol libraries from All About Circuits or community repositories. Both represent the exact same truth table logic; only the visual geometry differs.
What is the difference between a truth table and a state table?
A truth table maps combinatorial logic: the output depends only on the current inputs (e.g., AND, OR, XOR gates). A state table maps sequential logic: the output depends on both the current inputs and the previous state of the system (e.g., flip-flops, registers, and finite state machines). State tables include additional columns for 'Current State' and 'Next State', which truth tables do not require.
