A truth table for a boolean expression is the definitive lookup chart for digital logic. It maps every possible combination of binary inputs ($2^n$ states) to a single, deterministic output. While software developers use these tables to optimize conditional statements in firmware, hardware engineers and bench technicians rely on them to design combinatorial logic, debug state machines, and verify signal integrity on the oscilloscope.
Below is the master reference for 2-input logic gates, followed by the practical realities of applying these ideal mathematical models to physical silicon like the 74HC or CD4000 series ICs.
Standard Logic Gate Truth Tables (IEEE/IEC Reference)
The following data table defines the standard boolean expressions for 2-input gates. The logic states and symbolic definitions align with IEEE Std 91-1984 and IEC 60617-12 standards for graphic symbols for logic functions.
| Input A | Input B | AND (A·B) | NAND (A·B)' | OR (A+B) | NOR (A+B)' | XOR (A⊕B) | XNOR (A⊕B)' |
|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
| 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 |
| 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 |
Which Column Applies to Your Circuit?
The standard output columns (AND, OR, XOR) assume a push-pull output stage, where the IC actively drives the pin to VCC (1) or GND (0). If you are using an IC with open-drain or open-collector outputs—such as the 74HC03 (Quad 2-Input NAND with Open-Drain) or an ESP32 GPIO configured as open-drain—the standard '1' column does not apply directly.
For open-drain outputs, a logic '0' actively pulls the line to GND, but a logic '1' leaves the pin floating (High-Z). You must install an external pull-up resistor (typically 4.7kΩ to 10kΩ for I2C lines, or 1kΩ for general logic) to achieve the '1' state. Without it, your multimeter will read a floating voltage, and the downstream gate will interpret it as noise.
Modifying the Base Value: Derating and Don't-Care States
In power systems, derating reduces wire ampacity based on temperature. In digital logic, we 'derate' the ideal truth table based on voltage thresholds and Karnaugh map optimizations.
Voltage Threshold Derating
The truth table assumes '1' is exactly VCC and '0' is exactly 0V. Real silicon uses threshold windows defined in the datasheet as $V_{IH}$ (Input High Voltage) and $V_{IL}$ (Input Low Voltage). For a 74HC series IC running at 5V, $V_{IH}$ is typically 3.15V and $V_{IL}$ is 1.35V.
If your power supply sags under load and your 'High' signal only reaches 2.8V, the downstream gate will not register a '1'. The base value of the truth table is effectively derated to 'Unknown' or '0' because the physical voltage failed to cross the $V_{IH}$ threshold. Always verify logic levels with an oscilloscope, not just a multimeter's average DC reading.
Don't-Care (X) and High-Z States
When simplifying boolean expressions using Karnaugh maps, you will encounter Don't-Care (X) conditions. These are input combinations that will never occur in your specific application, allowing you to assign them a '0' or '1' to minimize logic gates.
However, in physical CMOS silicon (like the CD4011 or 74HC00), never leave an input pin floating to achieve an 'X' state. A floating CMOS input acts as an antenna, picking up electromagnetic noise. This causes the internal MOSFETs to rapidly switch on and off, resulting in 'shoot-through' current that can overheat and destroy the IC. Always tie unused inputs to VCC or GND via a resistor or direct trace.
What the Truth Table Cannot Tell You (Silicon Reality)
A boolean truth table is a purely mathematical construct. It operates in zero time and assumes infinite current capability. When you move from simulation to the workbench, the table fails to predict three critical failure modes:
The table says 1 AND 1 = 1. But if inputs A and B transition from 0 to 1 simultaneously, and B arrives 3 nanoseconds before A, the output will briefly glitch to 0 before settling at 1. In high-speed designs or clocked state machines, this 3ns glitch can falsely trigger a downstream flip-flop.
2. Metastability:
If you feed an asynchronous signal (like a mechanical pushbutton or an external sensor) directly into a clocked flip-flop, the input might violate the setup or hold time requirements. The output won't be a clean '0' or '1' as the table suggests; it will enter a metastable state, oscillating or hovering at $V_{CC}/2$ for several nanoseconds before resolving. Always use a 2-stage synchronizer for asynchronous inputs.
3. Fan-Out and Current Sinking ($I_{OL}$):
The table assumes an output can drive infinite inputs. In reality, a standard 74HC gate can only source or sink about 25mA. If you connect an AND gate output to five relays or high-current LEDs, the output voltage will droop, violating the logic threshold of any downstream digital ICs connected to the same net.
Quick-Jump Reference: Boolean Algebra Identities
When you need to simplify a complex boolean expression to reduce the physical IC count on your PCB, use these fundamental identities. This table is optimized for quick lookup when writing firmware logic or minimizing discrete gate layouts.
| Law / Identity | Boolean Expression | Practical Application |
|---|---|---|
| De Morgan's Law 1 | (A · B)' = A' + B' | Converts NAND logic into OR logic with inverted inputs; essential for optimizing PLC ladder logic or FPGA LUTs. |
| De Morgan's Law 2 | (A + B)' = A' · B' | Converts NOR logic into AND logic with inverted inputs. |
| Absorption | A + (A · B) = A | Eliminates redundant sensor checks in microcontroller 'if' statements, saving clock cycles. |
| Idempotent | A · A = A | Proves that tying both inputs of a 2-input AND gate together creates a functional buffer (or inverter if using NAND). |
| Complement | A · A' = 0 | Highlights why tying an input to its own inverted signal creates a permanent logic low (useful for forcing a reset). |
For deeper study on combinatorial logic and Karnaugh mapping, refer to the All About Circuits Digital Textbook chapter on boolean algebra. When selecting physical ICs to implement these tables, always consult the manufacturer's datasheet—such as the Texas Instruments Logic Family Overview—to verify $V_{IH}$, $V_{IL}$, and propagation delay specifications for your specific supply voltage.
