To find the total circuit resistance ($R_T$) in a series-parallel network, you must first calculate the equivalent resistance of the parallel branches, then add that result to any series components. In practical circuit design, pure series or pure parallel topologies are rarely used in isolation. Instead, we rely on series-parallel combinations to create stable bias networks, protect sensitive inputs, and manage fault conditions.

This guide walks through a real-world series-parallel sensor bias network, mapping node behavior under fault conditions, sizing actual E24-series components, and verifying the build on a breadboard.

Topology Description and Node Mapping

Let us define a practical series-parallel topology commonly used to interface an NTC thermistor with a microcontroller ADC. We will label three critical nodes:

  • Node A (Source): The 5V VCC rail.
  • Node B (Sense): The midpoint junction where the ADC reads voltage.
  • Node C (Ground): The 0V reference.

The configuration is as follows:

  • R1 (Series): Connected between Node A and Node B. Acts as the primary current limiter and upper voltage divider leg.
  • R2 (Sensor/Parallel Leg 1): Connected between Node B and Node C. This is our variable 10kΩ NTC thermistor.
  • R3 (Bleed/Parallel Leg 2): Connected in parallel with R2, between Node B and Node C. Acts as a pull-down to prevent floating nodes and limit maximum voltage swing.

To calculate the total circuit resistance, we first find the parallel equivalent of R2 and R3 ($R_{P}$), then add R1:

$R_{P} = \frac{R2 \times R3}{R2 + R3}$

$R_T = R1 + R_{P}$

Behavior and Fault Analysis Table

The table below maps exactly what happens to the total circuit resistance and Node B voltage when individual elements fail. This data assumes a 5V source and nominal values of R1 = 4.7kΩ, R2 = 10kΩ, and R3 = 47kΩ.

Fault Condition Parallel Eq. ($R_P$) Total Resistance ($R_T$) Node B Voltage Circuit State / Consequence
Nominal (25°C) 8.24 kΩ 12.94 kΩ 3.18 V Normal operation. ADC reads stable bias.
R1 Open 8.24 kΩ ∞ (Infinite) 0.00 V Circuit broken. Node B pulled to GND via R2||R3.
R1 Short 8.24 kΩ 8.24 kΩ 5.00 V Max current draw (0.6mA). ADC reads rail voltage.
R2 Open 47.0 kΩ 51.7 kΩ 4.54 V Thermistor disconnected. R3 prevents Node B from floating.
R2 Short 0 Ω 4.7 kΩ 0.00 V Thermistor shorted. R1 limits max current to 1.06mA.
R3 Open 10.0 kΩ 14.7 kΩ 3.40 V Bleed resistor fails. Circuit reverts to pure series divider.
R3 Short 0 Ω 4.7 kΩ 0.00 V Node B hard-tied to GND. ADC reads 0V permanently.
Safety Note: While a short in R2 or R3 drops the total circuit resistance to 4.7kΩ (drawing ~1.06mA from a 5V source), this is harmless for standard logic supplies. However, if Node A were tied to a 24V industrial PLC supply, that same short would push 5.1mA and dissipate 122mW in R1. Always verify $I^2R$ power dissipation against your resistor's wattage rating (typically 1/4W or 250mW for through-hole) when evaluating short-circuit extremes.

Why This Topology Over the Alternatives?

When designing sensor interfaces, you might wonder why we do not just use a simple series voltage divider (R1 and R2 only) or a pure parallel network. The SparkFun Voltage Divider Tutorial covers basic series dividers, but real-world environments demand the series-parallel hybrid for three specific reasons:

  1. Floating Node Prevention (vs. Pure Series): If a pure series thermistor (R2) snaps off its breadboard or breaks internally, Node B becomes high-impedance. The microcontroller ADC will read ghost voltages induced by nearby EMI. Adding R3 in parallel guarantees Node B is pulled to a known state (near VCC) if R2 opens.
  2. Current Limiting (vs. Pure Parallel): If you placed R1 in parallel with R2, a short in the sensor would directly short the 5V rail to ground, tripping your bench supply's OCP or melting a trace. R1 must remain in series to act as the ballast.
  3. ADC Source Impedance Matching: Microcontroller ADCs (like the SAR ADC on an ATmega328P or ESP32) require a low-impedance source to charge their internal sample-and-hold capacitors. By calculating the Thevenin equivalent resistance looking into Node B, we ensure accurate readings.

For a deeper mathematical breakdown of reducing these networks, the All About Circuits textbook on series-parallel analysis provides excellent foundational theory.

Design Walkthrough: Sizing Real Components

Let us pick standard E24-series component values to bias a 10kΩ NTC thermistor (R2) for an ESP32 ADC (0-3.3V range, though we will run the divider at 3.3V for this specific design iteration to avoid clipping).

Step 1: Select the Parallel Bleed Resistor (R3)

We want R3 to be roughly 4 to 5 times the nominal value of R2 so it does not excessively load the sensor, but remains low enough to prevent floating.

Choice: R3 = 47kΩ.

Step 2: Calculate Parallel Equivalent ($R_P$)

$R_P = \frac{10k \times 47k}{10k + 47k} = \frac{470}{57} = 8.24k\Omega$

Step 3: Select the Series Resistor (R1)

To center the voltage at Node B near the middle of the 3.3V ADC range (approx 1.65V) at room temperature, R1 should be close to $R_P$.

Choice: R1 = 8.2kΩ (Standard E24 value). Let us recalculate $R_T$ and Node B voltage with this updated R1.

  • $R_T = 8.2k + 8.24k = 16.44k\Omega$
  • $I_{total} = \frac{3.3V}{16.44k\Omega} = 0.20mA$
  • $V_{NodeB} = I_{total} \times R_P = 0.20mA \times 8.24k\Omega = 1.65V$ (Perfect midpoint).

Step 4: Verify Thevenin Equivalent Resistance ($R_{th}$)

The ESP32 ADC is notoriously non-linear if the source impedance is too high. The Thevenin resistance looking into Node B (with the 3.3V source shorted to GND) is R1 || R2 || R3.

$\frac{1}{R_{th}} = \frac{1}{8.2k} + \frac{1}{10k} + \frac{1}{47k}$

$R_{th} \approx 4.15k\Omega$

Because 4.15kΩ is well below the 10kΩ maximum recommended source impedance for most SAR ADCs, this topology will yield clean, stable samples without requiring an external op-amp buffer.

Pro-Tip: When ordering resistors for precision sensor networks, skip the standard 5% carbon film parts. Spend the extra $0.50 for 1% metal film resistors (e.g., Vishay MRS25 series). A 5% tolerance on R1 could skew your Node B baseline voltage by over 100mV, ruining your temperature calibration curve before you even write a line of code.

Breadboard Testing and Verification Steps

Do not just plug the components in and upload your code. Verify the physical total circuit resistance first to catch wiring errors that could fry your microcontroller pin. You will need a DMM (like a Brymen BM235 or Fluke 117) and your populated breadboard.

  1. De-energize the Board: Ensure the breadboard power rails are completely disconnected. Measuring resistance on a live circuit will yield garbage data and can blow the fuse inside your multimeter.
  2. Verify Individual Components: Set your DMM to the appropriate resistance range (e.g., 200kΩ). Measure R1, R2, and R3 individually before inserting them. Confirm R1 reads ~8.2kΩ and R3 reads ~47kΩ. (R2 will vary based on ambient temperature and body heat if you hold it too long).
  3. Measure the Parallel Branch ($R_P$): Insert R2 and R3 into the breadboard so they share the same ground bus and the same Node B row. Place your DMM probes across the Node B row and the ground bus. You should read exactly 8.24kΩ. If you read 10kΩ or 47kΩ, one of the resistor legs is not making contact with the internal breadboard leaf springs.
  4. Measure Total Circuit Resistance ($R_T$): Insert R1 so one leg is in the Node B row and the other is in the VCC rail row. Place your red probe on the VCC rail row (Node A) and your black probe on the ground bus (Node C). The meter should display 16.44kΩ.
    • Troubleshooting: If you read ~8.2kΩ, R2 and R3 are accidentally shorted to ground, or R1 is shorted. If you read 'OL' (Overlimit), there is a break in the series path.
  5. Live Voltage Verification: Connect your 3.3V power supply. Switch the DMM to DC Volts. Measure between Node B and Ground. You should see 1.65V (±50mV). Pinch the thermistor (R2) with your fingers; the voltage should smoothly drop as the thermistor's resistance decreases with body heat.

By mapping the topology, calculating the exact total circuit resistance, and verifying the Thevenin limits, you bridge the gap between abstract schematic theory and a reliable, noise-free physical prototype.