The Math of Heat: Junction-to-Ambient Thermal Resistance
When a semiconductor dissipates power, the heat must travel from the silicon die to the surrounding air. This path is modeled as a series of thermal resistances, measured in °C/W. If you do not calculate this path, your component will silently cook itself. The fundamental equation for junction temperature ($T_J$) is:
$T_J = T_A + P_D(R_{\theta JC} + R_{\theta CS} + R_{\theta SA})$
- $T_A$: Ambient temperature (°C)
- $P_D$: Power dissipation (W)
- $R_{\theta JC}$: Junction-to-case thermal resistance (internal to the package)
- $R_{\theta CS}$: Case-to-sink thermal resistance (interface material)
- $R_{\theta SA}$: Sink-to-ambient thermal resistance (the heatsink and airflow)
According to All About Circuits, treating heat flow like an Ohm's Law circuit ($V = I \times R$ becomes $\Delta T = P \times R_{\theta}$) is the most reliable way to predict operating temperatures. If your calculated $T_J$ exceeds the silicon limit, the part will eventually fail, regardless of what the "maximum ratings" table implies about short-term survival.
Derating Curves and Temperature Coefficient Resistivity
A component's ability to shed heat is not static; it changes as materials heat up. This is where the temperature coefficient resistivity (TCR) becomes critical. TCR defines how much a material's electrical resistance changes per degree of temperature change, typically expressed in ppm/°C (parts per million per degree Celsius).
Power MOSFETs have a highly positive temperature coefficient for their on-resistance ($R_{DS(on)}$). As the die heats up, $R_{DS(on)}$ increases by roughly 0.5% to 1.0% per °C. If you calculate conduction losses ($I^2R$) using the 25°C datasheet value, your actual heat dissipation at 100°C will be 50% to 100% higher than your math predicted, shifting your thermal equilibrium dangerously upward.
This positive feedback loop directly impacts how you read a derating curve. A derating curve shows the maximum allowable power dissipation dropping linearly as ambient temperature rises above 25°C. The slope of this line is exactly $1 / R_{\theta JA}$.
| Material / Component | TCR (ppm/°C) | Thermal Management Impact |
|---|---|---|
| Copper (Trace/Busbar) | +3,900 | Increases $I^2R$ trace heating at high ambient temps. |
| Silicon MOSFET $R_{DS(on)}$ | +5,000 to +10,000 | Aids parallel current sharing, but raises total conduction losses. |
| Metal Foil Precision Resistor | ± 2 to ± 5 | Negligible resistance drift; ideal for current sense shunts. |
| NTC Thermistor | -30,000 to -50,000 | Resistance drops as it heats, risking thermal runaway if unbiased. |
How hot is too hot? While most silicon power devices boast a maximum junction temperature ($T_{J(max)}$) of 150°C or 175°C, operating at this limit is a death sentence for long-term reliability. A practical engineering rule is to derate your design so $T_J$ never exceeds 100°C to 110°C under worst-case continuous load. For every 10°C you reduce the operating temperature below the maximum, you roughly double the expected lifespan of the semiconductor.
Heatsink Selection: A Wattage-Based Sizing Example
Let's size a heatsink for an IRF3205 MOSFET in a TO-220 package dissipating a continuous 15W inside an enclosed project box where the ambient air ($T_A$) reaches 40°C. We want to keep $T_J$ under 125°C.
- Calculate maximum allowable thermal resistance:
$R_{\theta JA(max)} = (T_J - T_A) / P_D = (125 - 40) / 15 = 5.66 °C/W$. - Subtract known internal resistances:
The TO-220 $R_{\theta JC}$ is typically 1.5 °C/W.
We will use a Bergquist Sil-Pad 400V thermal interface material, which gives an $R_{\theta CS}$ of about 0.5 °C/W at this pressure and wattage. - Solve for the required heatsink ($R_{\theta SA}$):
$R_{\theta SA} = 5.66 - (1.5 + 0.5) = 3.66 °C/W$.
We need a heatsink with a sink-to-ambient resistance of 3.66 °C/W or lower. Looking at DigiKey's thermal management guides and manufacturer catalogs, the Aavid (Boyd) 577202B00000G is an extruded aluminum TO-220 heatsink rated at approximately 3.5 °C/W in natural convection. This passes our math with a 0.16 °C/W margin.
What do airflow and enclosure changes buy you?
If you add a small 40mm fan pushing 1 m/s of air across that same Aavid heatsink, the $R_{\theta SA}$ plummets to roughly 1.8 °C/W, allowing you to dissipate nearly 28W while maintaining the same 125°C junction limit. Conversely, if you seal the enclosure without providing a thermal path from the heatsink to the outside chassis, the "ambient" air inside the box will rapidly rise well past 40°C, invalidating your initial $T_A$ assumption and causing thermal failure.
Failure Signatures of Thermal Stress
When thermal management fails, components rarely just stop working instantly; they degrade in specific, measurable ways:
- Electromigration: At high current densities and elevated temperatures (usually >100°C), metal atoms in the silicon interconnects are physically pushed by electron flow, eventually creating open circuits or shorting adjacent traces.
- Solder Joint Creep: Repeated thermal cycling causes the coefficient of thermal expansion (CTE) mismatch between the silicon die, the leadframe, and the PCB to flex the solder joints. Over time, this mechanical fatigue creates micro-cracks, increasing contact resistance and generating even more localized heat.
- Parametric Shift: In analog circuits, the temperature coefficient resistivity of standard thick-film resistors (often ±200 ppm/°C) will cause timing constants in RC networks or gain settings in op-amp feedback loops to drift as the board heats up, leading to out-of-spec performance long before a catastrophic meltdown occurs.
Frequently Asked Questions
How does the temperature coefficient of resistivity cause thermal runaway in battery packs?
In lithium-ion cells, internal resistance generally decreases as temperature rises (a negative temperature coefficient in certain operational bands). If a cell begins to overheat due to high discharge currents, its internal resistance drops, which causes it to draw even more current from parallel cells. This increased current generates more $I^2R$ heat, further lowering resistance in a positive feedback loop that can lead to venting or fire. This is why battery management systems (BMS) monitor individual cell temperatures and disconnect the pack before the negative TCR region triggers a runaway event.
Why do precision resistors specify a low temperature coefficient of resistivity in ppm/°C?
In precision measurement, current shunts, and DAC reference networks, the physical temperature of the resistor will change due to both ambient shifts and self-heating ($I^2R$). A standard 1% carbon film resistor might have a TCR of ±500 ppm/°C, meaning a 50°C temperature rise changes its resistance by 2.5%—completely destroying the accuracy of a 12-bit ADC. Precision metal foil or bulk metal element resistors are engineered with opposing TCR materials that cancel each other out, achieving TCR values as low as ±0.2 ppm/°C, ensuring the resistance remains stable regardless of thermal load.
Can a negative temperature coefficient resistivity be used for overcurrent protection?
Not directly for overcurrent, but a positive temperature coefficient (PTC) is exactly how resettable fuses work. A PTC thermistor has a relatively flat, low resistance at room temperature. When an overcurrent event occurs, the $I^2R$ heating causes the polymer or ceramic matrix to expand past a critical threshold, suddenly spiking the resistance by several orders of magnitude. This high-resistance state chokes off the current, protecting the circuit. Once the fault is removed and the part cools, the resistance drops back down, resetting the fuse.
