Symmetric Stripline Calculator Formulas: Impedance, Delay, and Worked Examples

When you open a stripline calculator in your PCB stackup tool, it is solving a specific set of quasi-TEM transmission line equations. Unlike microstrip, where the electric field fringes into the air above the board, a symmetric stripline is fully embedded in a homogeneous dielectric between two ground planes. This means the effective dielectric constant is simply the relative permittivity of the substrate material, making the math cleaner but the physical stackup constraints much tighter.

The direct answer for the characteristic impedance (Z₀) of a centered, symmetric stripline is given by the industry-standard approximation (valid when W/(b-t) < 0.35):

Z₀ = (60 / √ε_r) × ln[ 4b / (0.67 × π × (0.8W + t)) ]

Below, we break down every variable, map out real-world FR4 stackups, and run through bench-level worked examples with strict unit tracking so you can verify your field solver's output by hand.

The Core Stripline Impedance Formula & Symbol Definitions

This formula assumes a homogeneous dielectric, negligible copper surface roughness (which matters at mmWave frequencies but not at sub-6 GHz digital edges), and a perfectly centered trace. If your trace is offset closer to one ground plane (asymmetric stripline), the capacitance increases and this formula will overestimate your impedance. For standard RF and high-speed digital design, symmetric is the target.

Table 1: Stripline Formula Symbol Definitions and Typical Ranges

Symbol	Parameter	Standard Unit	Typical FR4 Range	Notes & Assumptions
Z0	Characteristic Impedance	Ohms (Ω)	40 - 100 Ω	Target is usually 50Ω (RF) or 85-100Ω (differential digital).
εr	Relative Permittivity (Dk)	Dimensionless	3.0 - 4.5	Use the design Dk at your target frequency, not the 1 MHz datasheet value.
b	Total Dielectric Thickness	mils or mm	10 - 60 mils	Distance between the two ground planes. Not the distance to one plane.
W	Trace Width	mils or mm	4 - 25 mils	Physical etched width. Account for fabrication tolerances (usually ±0.5 mil).
t	Trace Thickness	mils or mm	0.7 - 1.4 mils	0.5 oz copper ≈ 0.7 mils; 1.0 oz copper ≈ 1.4 mils. Includes plating.

Because stripline is fully enclosed, the propagation delay (t_pd) is entirely dependent on the substrate material, with no air-fringing penalty:

t_pd = 85 × √ε_r (in picoseconds per inch)

Real-World FR4 Stackup Parameters

Before running the math, you need a realistic stackup. A common mistake is assuming you can achieve 50Ω stripline on a standard 0.062" 4-layer board without checking the core thicknesses. The table below provides verified starting points for symmetric stripline designs using standard Megtron-6 or FR408HR materials (ε_r ≈ 3.6 at 5 GHz) and 1 oz copper (t = 1.4 mils).

Table 2: Data-Dense Stackup Targets for 50Ω Symmetric Stripline

Stackup Type	Total Dielectric b (mils)	Required Trace Width W (mils)	Resulting Z0 (Ω)	Propagation Delay (ps/in)
6-Layer (L3 routed)	20.0	7.2	50.1	161
8-Layer (L3/L6 routed)	24.0	9.4	49.9	161
10-Layer (L4/L7 routed)	16.0	4.8	50.2	161
12-Layer (L5/L8 routed)	30.0	13.1	49.8	161

Notice the trend: to maintain 50Ω as the dielectric cavity (b) shrinks, the trace width (W) must drop proportionally. If your fab house has a minimum trace width limit of 4 mils, you cannot route 50Ω stripline in a cavity thinner than roughly 14 mils.

Worked Examples with Strict Unit Tracking

Let's run two calculations. The most critical rule in transmission line math is that the argument inside the natural logarithm must be dimensionless. Therefore, b, W, and t must all be expressed in the exact same unit (we will use mils) before dividing them.

Problem 1: Calculating Impedance from Physical Dimensions

Given: A 6-layer board with a total dielectric cavity b = 20 mils, substrate ε_r = 4.2 (standard FR4), 0.5 oz copper (t = 0.7 mils), and an etched trace width W = 8.0 mils. Find Z₀.

1. Verify Units: b (20), W (8), and t (0.7) are all in mils. The ratio will be dimensionless.
2. Calculate the log denominator: 0.67 × π × (0.8 × 8.0 + 0.7) = 2.1049 × (6.4 + 0.7) = 2.1049 × 7.1 = 14.945
3. Calculate the log numerator: 4 × 20 = 80
4. Evaluate the log argument: 80 / 14.945 = 5.353
5. Take the natural log: ln(5.353) = 1.6776
6. Calculate the leading multiplier: 60 / √4.2 = 60 / 2.0494 = 29.277
7. Final Multiplication: Z₀ = 29.277 × 1.6776 = 49.11 Ω

Result: 49.1 Ω is well within the standard ±10% tolerance for a 50 Ω target.

Problem 2: Calculating Required Trace Width for a Target Impedance

Given: You are designing an RF filter on a low-loss dielectric (ε_r = 3.5). The cavity thickness b is fixed at 30 mils by the laminate vendor. You are using 1 oz copper (t = 1.4 mils). You need exactly Z₀ = 75 Ω. Find W.

1. Calculate the exponent term (E): E = (Z₀ × √ε_r) / 60 = (75 × √3.5) / 60 = (75 × 1.8708) / 60 = 2.3385
2. Exponentiate: e^2.3385 = 10.364
3. Set up the width equation: 0.8W + t = (4b) / (0.67 × π × 10.364)
4. Solve the right side: (4 × 30) / (2.1049 × 10.364) = 120 / 21.815 = 5.501
5. Subtract trace thickness (t): 0.8W = 5.501 - 1.4 = 4.101
6. Divide by 0.8: W = 4.101 / 0.8 = 5.13 mils

Result: You must specify a 5.13 mil trace width to your fab house to hit 75 Ω in this stackup.

Rearranged Forms, Fatal Unit Mistakes, and Realistic Magnitudes

Field solvers like Si9000 or Polar are great, but knowing the algebraic rearrangements lets you debug bad stackup files in minutes. Here are the isolated forms for the two most common unknown variables:

• Solving for Trace Width (W):
  W = 1.25 × [ (4b) / (0.67 × π × e^{(Z₀ × √ε_r / 60)}) - t ]
• Solving for Cavity Thickness (b):
  b = [ 0.67 × π × (0.8W + t) × e^{(Z₀ × √ε_r / 60)} ] / 4

Three Unit Mistakes That Break the Math

When manual calculations diverge from your stripline calculator software, it is almost always due to one of these three errors:

1. Confusing b with h: In microstrip, h is the distance from the trace to the single ground plane. In symmetric stripline, b is the total distance between the top and bottom ground planes. If your prepreg is 10 mils and your core is 10 mils, b = 20 mils. Plugging in 10 will result in an impedance calculation that is drastically too low.
2. Mixing Metric and Imperial in the Logarithm: If b is in millimeters but W and t are in mils, the ratio inside the ln() function is no longer dimensionless. The math will execute, but the output will be garbage. Convert everything to mils (or everything to mm) before touching the calculator.
3. Using Absolute Permittivity: The formula requires ε_r (the dimensionless dielectric constant, like 4.2). Do not multiply by the vacuum permittivity constant (ε₀ ≈ 8.854 × 10^-12 F/m). If your ε_r input is on the order of 10^-11, you are using the wrong constant.

What Do Realistic Answer Magnitudes Look Like?

If your calculator spits out a number outside these boundaries, your stackup inputs are likely physically impossible for standard PCB fabrication:

• Impedance (Z₀): Should fall between 40 Ω and 100 Ω. Hitting 30 Ω requires a trace so wide it acts like a parallel plate capacitor; hitting 120 Ω requires a trace so narrow (under 2 mils) that etching tolerances will destroy your yield.
• Trace Width (W): Typically 4 to 25 mils for standard digital/RF boards.
• Propagation Delay (t_pd): For standard laminates (ε_r = 3.0 to 4.5), expect 145 to 180 ps/inch. If your calculator shows 250 ps/inch, you accidentally input the dielectric constant of water or a ceramic substrate.

For deeper reading on high-frequency laminate behavior and fabrication tolerances, the All About Circuits guide on transmission lines provides excellent foundational context on why stripline yields better EMI performance than microstrip at the cost of tighter routing constraints.