The symbols of logic gates fall into two global standards: the ANSI/IEEE 'distinct shape' symbols (standard in the US, hobbyist electronics, and military schematics) and the IEC 60617 'rectangular' symbols (standard in Europe, industrial automation, and modern CAD tools). If you are reading a US datasheet or an Arduino tutorial, expect ANSI shapes. If you are programming a European PLC or reading an IEC-standard textbook, expect IEC rectangles. Below is the direct mapping for both standards, alongside the physical IC part numbers you will actually solder to your board.
The Complete Logic Gate Symbol Reference Table
Use this spec-sheet-table to cross-reference schematic symbols with physical 74HC (High-speed CMOS) and CD4000 (Standard CMOS) integrated circuits. Assume standard 14-pin or 16-pin DIP packages unless otherwise noted.
| Gate Type | ANSI/IEEE Symbol Description | IEC 60617 Symbol Description | Boolean Expression | Common IC Part Number |
|---|---|---|---|---|
| AND | D-shaped flat back, curved front | Rectangle with '&' qualifier | A · B | 74HC08 / CD4081 |
| OR | Curved back, pointed front | Rectangle with '≥1' qualifier | A + B | 74HC32 / CD4071 |
| NOT (Inverter) | Triangle with output bubble | Rectangle with '1' and output bubble | A' | 74HC04 / CD4069 |
| NAND | D-shape with output bubble | Rectangle with '&' and output bubble | (A · B)' | 74HC00 / CD4011 |
| NOR | Curved OR shape with output bubble | Rectangle with '≥1' and output bubble | (A + B)' | 74HC02 / CD4001 |
| XOR | OR shape with extra curved input line | Rectangle with '=1' qualifier | A ⊕ B | 74HC86 / CD4030 |
| XNOR | XOR shape with output bubble | Rectangle with '=1' and output bubble | (A ⊕ B)' | 74HC266 / CD4077 |
Regional Standards and 'Rows People Get Wrong'
The divergence in the symbols of logic gates stems from two different design philosophies. The US-based ANSI/IEEE Std 91 uses distinct geometric shapes so you can identify the gate type at a glance without reading the text inside it. The European IEC 60617 standard uses uniform rectangles because they scale much better when drawing complex programmable logic arrays (PLAs) and microprocessor architectures, relying on internal alphanumeric tags (like '&' or '≥1') to define the logic.
The Rows People Get Wrong
- NAND vs. NOR (ANSI): The ANSI shapes are distinct (flat back for AND/NAND vs. curved back for OR/NOR). However, on a poorly printed or heavily photocopied schematic, the curve of the NOR gate flattens out, making it look identical to a NAND gate. Always check the input side curvature, not just the output bubble.
- XOR vs. XNOR: The inversion bubble on the XNOR output is tiny. In dense schematics, it easily blends into the intersection of the output wire and the next component. If a circuit is behaving erratically, verify whether the designer intended an XOR or XNOR by checking the IC part number (e.g., 74HC86 vs 74HC266) rather than trusting the schematic ink.
- Buffer vs. Inverter: A non-inverting buffer looks exactly like a NOT gate but lacks the output bubble. Buffers (like the 74HC125) are used for current drive and signal isolation, not logic inversion. Missing that missing bubble will cause you to invert your enable signals.
Practical Pinouts and Voltage Thresholds
Knowing the symbols of logic gates is only half the battle; you must also understand the electrical realities of the silicon. Let us look at a worked example using the Texas Instruments SN74HC08 (Quad 2-Input AND Gate).
The 74HC08 contains four independent AND gates in a single 14-pin package. The standard pinout is:
- Pin 14: VCC (Supply Voltage, 2.0V to 6.0V)
- Pin 7: GND (Ground)
- Pins 1, 2 (Inputs) & 3 (Output): Gate A
- Pins 4, 5 (Inputs) & 6 (Output): Gate B
- Pins 9, 10 (Inputs) & 8 (Output): Gate C
- Pins 12, 13 (Inputs) & 11 (Output): Gate D
The Voltage Threshold Trap
A common bench mistake is assuming a 'logic high' is anything above 2.5V on a 5V system. According to the NXP and TI datasheets for the 74HC family running at 5V, the input voltage thresholds are strictly defined:
- V_IL (Max Low Input): 1.35V (Anything below this is a guaranteed '0')
- V_IH (Min High Input): 3.15V (Anything above this is a guaranteed '1')
If you interface a 3.3V microcontroller (like an ESP32) directly to a 5V 74HC08, the 3.3V output sits comfortably above the 3.15V V_IH threshold, but with very little noise margin. If your wiring is long or noisy, the AND gate might misread the signal. For robust designs, either run the 74HC08 at 3.3V (which lowers the V_IH to ~2.1V) or use a dedicated level shifter like the 74LVC245.
Frequently Asked Questions
What are the symbols of logic gates used in PLC programming?
In industrial Programmable Logic Controller (PLC) programming, specifically within IEC 61131-3 Ladder Logic, the symbols of logic gates are rarely drawn as traditional schematic shapes. Instead, they are represented as 'contacts' and 'coils'. A normally open (NO) contact acts as an AND gate when placed in series, and an OR gate when placed in parallel. A normally closed (NC) contact acts as a NOT gate (inverter). If you are looking at Function Block Diagram (FBD) programming in a PLC, the software will default to the IEC 60617 rectangular symbols (e.g., rectangles with '&' for AND).
How do I read the symbols of logic gates on a faded schematic?
When schematic ink degrades, the output inversion bubbles (indicating NAND, NOR, or XNOR) are the first to vanish. Do not rely on visual guessing. Cross-reference the symbol's input/output pin numbers with the Bill of Materials (BOM) or the physical IC printed on the PCB. If the IC is a 74HC00, it is a NAND gate, regardless of whether the schematic bubble is visible. If the IC part number is also missing, isolate the chip from the circuit, apply VCC/GND, and use a logic probe or multimeter to build a 4-row truth table to definitively identify the gate.
Why do the symbols of logic gates look different in European textbooks?
European textbooks use the IEC 60617 standard, which mandates rectangular shapes for all logic gates. The rationale is standardization and scalability. In complex VLSI (Very Large Scale Integration) design and modern FPGA architectures, drawing distinct D-shapes and curved OR-shapes becomes visually chaotic and wastes CAD space. The IEC standard solves this by using a uniform box and placing the logic qualifier (like '≥1' for OR, or '=1' for XOR) inside the box. While it requires reading the text inside the symbol, it makes drawing 64-bit bus logic and complex state machines significantly cleaner.
