The standard ANSI/IEEE symbol for a NAND gate is a D-shaped AND gate with a small inversion circle (bubble) at the output. The IEC standard uses a rectangular block with an ampersand (&) inside and an output bubble. In practice, a NAND gate outputs a LOW signal only when all of its inputs are HIGH; otherwise, the output is HIGH. Below is the complete reference data you need to read schematics and wire physical ICs on the bench.
Standard Logic Symbols & Truth Table Reference
Different engineering disciplines and regions rely on distinct graphic standards. While the underlying Boolean logic remains identical, the visual representation changes depending on whether you are reading a US military-spec schematic, a modern European IEC diagram, or legacy industrial prints. Use this table to decode the symbol for NAND logic across standards.
| Standard Body | Visual Description | Boolean Expression | Common IC Part Numbers |
|---|---|---|---|
| ANSI/IEEE (Std 91-1984) | D-shape (flat left back, curved right front) with a small circle on the output line. | Y = NOT (A AND B) or Y = A · B | 74HC00, 74LS00, SN7400 |
| IEC 60617-12 | Rectangular block with an '&' symbol inside and a small circle on the output line. | Y = NOT (A AND B) | CD4011, HEF4011, MC14011 |
| DIN (Legacy European) | Rectangular block with an '&' and a small triangle or line indicating inversion (rarely used in new designs). | Y = A ∧ B (with overline) | Obsolete / Legacy Siemens |
| De Morgan Equivalent | Curved-back OR shape with inversion bubbles on all inputs and no bubble on the output (Negative-OR). | Y = NOT A OR NOT B | Same physical ICs as above |
14-Pin DIP Pinouts & Regional Standard Variants
When moving from schematic symbols to physical breadboarding, you need the exact pinout. The vast majority of quad 2-input NAND gates come in a 14-pin Dual In-line Package (DIP). The pinout is standardized across almost all manufacturers (Texas Instruments, Nexperia, ON Semiconductor), regardless of whether the silicon is TTL (74-series) or CMOS (4000-series).
Standard Quad 2-Input NAND Pinout (14-Pin DIP):
- Pin 14: VCC (Positive Supply)
- Pin 7: GND (Ground)
- Gate 1: Inputs on Pins 1 & 2, Output on Pin 3
- Gate 2: Inputs on Pins 4 & 5, Output on Pin 6
- Gate 3: Inputs on Pins 9 & 10, Output on Pin 8
- Gate 4: Inputs on Pins 12 & 13, Output on Pin 11
Which standard applies to you? If you are working in the US, defense, or aerospace sectors, or reading textbooks published by All About Circuits, you will predominantly encounter the ANSI/IEEE D-shape symbols. If you are working with European industrial automation, PLC schematics, or modern IEC-compliant architectural drawings, expect the rectangular IEC blocks. Always check the title block of the schematic for the governing standard (e.g., 'IEC 60617' or 'IEEE 91').
Symbols and Schematic Rows People Get Wrong
Even experienced technicians misread logic diagrams when symbols are combined or altered. Here are the most common schematic traps involving NAND gates:
- Confusing the Bubble Placement (Active-Low vs. Inversion): A bubble on the output of a D-shape means the gate is a NAND (it inverts the AND result). However, if you see bubbles on the inputs of an OR-shape gate, that is logically identical to a NAND gate (De Morgan's Theorem). Designers use the 'Negative-OR' symbol to indicate that the inputs are active-low triggers. The physical IC is the same, but the schematic intent is different.
- Mixing Up NAND and NOR Shapes: The NAND symbol uses a D-shape (flat back, curved front). The NOR symbol uses a curved-back shape (like a shield or a spaceship). If the back of the gate is curved inward, it is an OR/NOR family gate, not an AND/NAND family gate, regardless of the output bubble.
- Assuming Unused Inputs Can Float: In schematic diagrams, you might see a NAND gate with only one input drawn, or an unused gate in a 14-pin package left unconnected. In CMOS logic (like the CD4011), floating inputs act as antennas, picking up mains hum and causing the gate to oscillate, which leads to massive current draw and overheating. Always tie unused NAND inputs to VCC or tie them to the used input.
Bench Testing: Identifying Faded or Unmarked NAND ICs
When salvaging components or repairing legacy hardware, you will inevitably encounter a 14-pin DIP IC with a faded, scratched, or completely missing top marking. How do you safely verify it is a NAND gate without a part number?
Assuming the IC is not physically cracked, you can deduce its function using a multimeter and a basic logic probe or jumper wires. Refer to the Texas Instruments SN74HC00 datasheet for standard electrical characteristics if you need exact voltage thresholds.
- Identify Power Pins: On 95% of 14-pin logic ICs, Pin 14 is VCC and Pin 7 is GND. Apply 5V DC to Pin 14 and ground Pin 7. (If the IC draws excessive current immediately, it is either wired backward, damaged, or not a standard logic gate).
- Test for NAND Truth Table: Pick a gate pair (e.g., Pins 1 and 2) and monitor the output (Pin 3) with your multimeter set to DC voltage.
- Tie Pin 1 to GND, Pin 2 to GND. Output (Pin 3) should read HIGH (~5V).
- Tie Pin 1 to 5V, Pin 2 to GND. Output should read HIGH (~5V).
- Tie Pin 1 to 5V, Pin 2 to 5V. Output should drop to LOW (<0.5V).
- Verify the Other Gates: Repeat this for the 4-5-6, 9-10-8, and 12-13-11 pin clusters. If all four gates exhibit this exact behavior, you have definitively identified a Quad 2-Input NAND gate, regardless of the missing silkscreen.
Frequently Asked Questions
What does the circle mean on a NAND logic symbol?
The small circle, universally called a 'bubble' or 'inversion circle', represents a logical NOT operation. On a NAND symbol, it indicates that the output of the internal AND operation is inverted. If the inputs dictate a HIGH output for a standard AND gate, the bubble flips it to a LOW output. In some schematic conventions, a bubble on an input line means that specific pin is 'active-low' (it triggers when pulled to ground).
How do I read a NAND gate pinout on a complex schematic?
Complex schematics often break a single 14-pin IC across multiple pages. Instead of drawing the whole 14-pin block, the designer will draw individual NAND symbols scattered through the circuit. Look for the IC designator (e.g., U4A, U4B, U4C, U4D). The letter (A, B, C, D) corresponds to the specific gate inside the package. Cross-reference the designator with the Bill of Materials (BOM) to find the physical IC part number, then apply the standard 14-pin DIP pinout rules outlined above to locate the physical pins on the board.
Is there a difference between the symbol for a NAND and a negative-OR gate?
Visually, yes; logically and physically, no. A NAND symbol is drawn as an AND gate with an output bubble. A negative-OR symbol is drawn as an OR gate with input bubbles. According to De Morgan's Theorem, these two configurations produce the exact same truth table. Engineers use the negative-OR symbol when they want to emphasize to the reader that the inputs are being triggered by low-voltage (active-low) signals, such as a reset button pulling a line to ground. Both symbols will map to the exact same physical pins on a 74HC00 or CD4011 IC.
