The standard ANSI/IEEE symbol for exclusive or (XOR) is a D-shaped curve with a convex back and an additional curved line parallel to the input side. In the IEC 60617 standard used heavily in Europe and industrial PLCs, the symbol is a simple rectangle with =1 printed inside. An XOR gate outputs a HIGH (1) only when its inputs are in different states (one HIGH, one LOW).
Complete XOR Symbol and Standard Reference
Different regions and engineering disciplines rely on distinct schematic standards. When reading a schematic or selecting a CAD library, you must match the symbol to the governing standard of the project. Below is the definitive reference for the symbol for exclusive or across global standards.
| Standard | Symbol Description | Boolean Expression | Common IC Examples | Primary Region / Usage |
|---|---|---|---|---|
| ANSI/IEEE Std 91 | Curved 'D' shape with a detached secondary arc on the input side. | A ⊕ B | TI SN74HC86, Nexperia 74LS86 | North America, Commercial PCB Design |
| IEC 60617 | Rectangular box with '=1' centered inside. |
A ⊕ B | NXP HEF4030B, ST CD4070 | Europe, Industrial Automation, PLCs |
| MIL-STD-806 | Similar to IEEE but often drawn with sharper angles and strict grid alignment. | A ⊕ B | 54HC86 (Military grade) | US Defense, Aerospace, Legacy Schematics |
| DIN 40700 (Legacy) | Rectangle with a '1' and an overline or specific function code (obsolete but seen in old EU prints). | A ⊕ B | Siemens SFL series (vintage) | Older German/European equipment manuals |
≥1' (meaning 1 or more inputs must be high). The '=1' marking strictly means exactly one input must be high, which is the definition of the symbol for exclusive or.
Rows People Get Wrong: XOR vs. OR and XNOR
When troubleshooting a board or drawing a schematic from memory, engineers frequently confuse the XOR symbol with its close relatives. Here is how to avoid the most common schematic and silkscreen misinterpretations.
- Missing the Back Arc (XOR vs. OR): The most frequent mistake in hand-drawn schematics is forgetting the detached input arc. Without that secondary arc, the symbol reverts to a standard OR gate. In a digital circuit, swapping an OR for an XOR will cause catastrophic logic errors in adders and parity checkers, as the OR gate will output a 1 when both inputs are high, while the XOR will output a 0.
- Missing the Output Bubble (XOR vs. XNOR): An Exclusive-NOR (XNOR) gate is simply an XOR gate with an inversion bubble on the output tail. If you are probing a 74HC266 XNOR IC but treat it as an XOR based on a hastily drawn schematic missing the bubble, your logic levels will be exactly inverted, leading to failed handshake protocols in UART or SPI debugging.
- Confusing XOR with a Half-Adder Block: In higher-level block diagrams, an XOR symbol is often used to represent the 'Sum' output of a half-adder. However, a half-adder also requires an AND gate for the 'Carry' output. Do not assume a single XOR IC pinout will handle both sum and carry operations.
Interpreting Faded Silkscreens and Missing Datasheets
On the bench, you will often encounter vintage equipment, repaired PCBs, or unmarked DIP chips where the silkscreen symbol for exclusive or is rubbed off, and the exact part number is illegible. Here is the safe, empirical method to verify an unknown 14-pin or 16-pin DIP is an XOR gate without relying on faded markings.
- Identify Power Pins: For standard 74-series (TTL/CMOS) 14-pin ICs, Pin 14 is VCC (5V) and Pin 7 is GND. For 4000-series CMOS, Pin 14 is VCC and Pin 7 is GND. Apply power using a current-limited bench supply set to 5V with a 100mA limit.
- Ground Unused Inputs: Critical for CMOS. If you are testing a 4000-series chip (like a CD4030), never leave inputs floating. Floating CMOS inputs act as antennas, picking up RF noise and causing the internal MOSFETs to oscillate, leading to thermal runaway that will physically crack the IC package. Tie all unused inputs to GND.
- The 'Tie-Together' Test: Using jumper wires, tie Input A and Input B of a single gate to GND (Logic 0). Measure the output with a multimeter or logic probe. It must read LOW (~0V).
- The 'Split' Test: Tie Input A to VCC (Logic 1) and Input B to GND (Logic 0). The output must now read HIGH (~5V).
- The 'Both-High' Test: Tie both Input A and Input B to VCC. The output must drop back to LOW. If the output stays HIGH when both inputs are HIGH, you are holding a standard OR gate (like a 74HC32), not an XOR gate.
For deeper verification, reference the All About Circuits XOR gate truth table to ensure the propagation delay matches the expected logic family (e.g., ~15ns for 74HC, ~50ns for CD4000 series).
Frequently Asked Questions
What is the boolean expression for the symbol for exclusive or?
The boolean expression is typically written as Y = A ⊕ B (using the circled plus operator). In standard algebraic form used in HDL coding (Verilog/VHDL) or when the XOR operator is unavailable, it is expressed as Y = (A · B') + (A' · B). This translates to: (A AND NOT B) OR (NOT A AND B). This algebraic expansion is exactly how you must wire an XOR gate if you are forced to build one out of discrete NAND or NOR gates on a breadboard.
How do I identify the symbol for exclusive or in PLC ladder logic?
In IEC 61131-3 compliant PLC programming (like Siemens TIA Portal or Allen-Bradley Studio 5000), you will rarely see the distinctive IEEE 'D' shape. Instead, the symbol for exclusive or is represented as a rectangular function block labeled XOR, or in basic ladder logic, it is constructed using a combination of Normally Open (NO) and Normally Closed (NC) contacts in parallel branches. Some modern IDEs also allow the use of the inequality operator <> or != in structured text to achieve the exact same XOR logical result.
Why does my EDA software show a different symbol for exclusive or?
EDA tools like Altium Designer, KiCad, and Eagle allow you to select your preferred schematic symbol library standard. If your symbol looks like a rectangle with '=1' instead of the curved D-shape, your library is set to IEC 60617. If it looks like a D-shape but lacks the detached back arc, you may have accidentally selected a custom or corrupted library part. Always verify the pin mappings (e.g., Pin 1/2 In, Pin 3 Out for Gate A on a standard quad 2-input XOR) against the manufacturer's datasheet, regardless of the graphical symbol rendered on your screen.
