For a 12-bit successive approximation A/D converter with a 5.0V reference, the Least Significant Bit (LSB) voltage step is exactly 1.22 mV, and an analog input of 2.5V converts to a digital code of 2048. The formula used is LSB = V_REF / 2^N. Substituting our values: 5.0V / 2^12 = 5.0 / 4096 = 0.0012207V. The digital code is V_IN / LSB = 2.5V / 0.0012207V = 2048.
The Core Conversion: Analog Voltage to Digital Code
Unlike flash ADCs that use hundreds of comparators in parallel, a successive approximation A/D converter (SAR ADC) relies on a binary search algorithm to digitize an analog signal. Inside the silicon, a sample-and-hold circuit captures the input voltage, and a successive approximation register (SAR) toggles the bits of an internal digital-to-analog converter (DAC) from the Most Significant Bit (MSB) down to the LSB. A high-speed comparator checks the internal DAC output against your input voltage at every step.
This architecture makes the SAR ADC the undisputed workhorse for medium-speed, high-precision industrial data acquisition. When you are designing a telemetry node or a precision multimeter, you are almost certainly using a SAR chip like the Texas Instruments ADS8688 or the Analog Devices AD7606. To translate the physical world into microcontroller logic, you must master the bit-to-voltage conversion.
The fundamental math is rigid. Your digital output code (D) is calculated as:
D = (V_IN / V_REF) * 2^N
Where V_IN is your measured analog voltage, V_REF is the ADC reference voltage, and N is the bit resolution. If V_IN equals V_REF, the output code is full-scale (e.g., 4095 for a 12-bit ADC, since it counts from 0 to 4095).
How Reference Voltage Shifts the Resolution
Readers transitioning from AC mains work often ask how the answer shifts for 120V vs 230V vs 3-phase systems, or when the conversion is meaningless if the power factor (PF) is unknown. In ADC theory, grid voltages and PF are entirely irrelevant. Instead, the single assumption that fixes your answer is the Reference Voltage (V_REF) and its stability. Just as AC real-power math is meaningless without a known PF, an ADC voltage-to-code conversion is completely meaningless if V_REF is floating, unregulated, or unknown. If your 5.0V reference is actually sagging to 4.8V under load, every single digital code you read will be mathematically skewed.
Furthermore, instead of shifting for 120V vs 230V, the ADC answer shifts based on its input range architecture. A unipolar 3.3V range yields different steps than a 5V range, and a bipolar ±10V range (common in industrial PLC inputs) shifts the LSB calculation to span a 20V total window, effectively doubling the voltage represented by each bit.
Below is a spec-sheet-table showing how a ±20% variance in a nominal 5.0V reference shifts the LSB size and the resulting digital code for a fixed 2.5V input on a 12-bit SAR ADC:
| V_REF (±20% Range) | LSB Size (12-Bit) | Digital Code for 2.5V Input |
|---|---|---|
| 4.0V | 0.976 mV | 2560 |
| 4.5V | 1.098 mV | 2276 |
| 5.0V (Nominal) | 1.220 mV | 2048 |
| 5.5V | 1.342 mV | 1862 |
| 6.0V | 1.464 mV | 1706 |
Real-World SAR ADC Edge Cases: Kickback and Settling
Theoretical formulas assume an ideal, zero-impedance voltage source. On the bench, this is never true. When the internal capacitor array of a SAR ADC switches during the binary search, it draws a high-frequency spike of current from the input pin. This is known as charge kickback.
If you are driving a 16-bit SAR ADC like the Analog Devices AD7606 directly from a high-impedance resistive voltage divider, the kickback will cause the voltage on the sample-and-hold capacitor to droop before the conversion completes. The result? Your 16-bit ADC will output noisy, non-linear data that effectively performs like a 10-bit ADC. According to Analog Devices architecture guides, you must either use a low-impedance source, add an external RC charge bucket filter, or insert a dedicated high-bandwidth ADC driver amplifier (like the THS4521) to supply the instantaneous charge required during the acquisition window.
Always verify your settling time. The input signal must settle to within 0.5 LSB of its final value before the SAR logic begins toggling bits. For a 16-bit ADC on a 5V range, 0.5 LSB is just 38 microvolts. Any dielectric absorption in your PCB capacitors or ringing in your trace inductance will destroy your resolution at this threshold.
Frequently Asked Questions
How does a successive approximation A/D converter differ from a Sigma-Delta ADC?
A SAR ADC captures a single snapshot of the voltage and resolves it in one conversion cycle, making it ideal for multiplexed channels and fast transient capture. A Sigma-Delta ADC, conversely, oversamples the signal at a massive rate and uses digital filtering to achieve ultra-high resolution (24-bit or 32-bit). As detailed in All About Circuits' ADC primers, choose a SAR ADC when you need to scan multiple channels quickly (up to a few MSPS) without phase delay; choose Sigma-Delta when you need extreme DC precision for a single, slow-moving signal like a strain gauge or thermocouple.
What happens if my input voltage exceeds the SAR ADC reference voltage?
If V_IN exceeds V_REF, the digital output will simply saturate at the maximum full-scale code (e.g., 4095 for 12-bit). However, if V_IN exceeds the absolute maximum analog input pin rating (often V_REF + 0.3V or VDD + 0.3V), the internal ESD protection diodes will forward-bias. This injects current into the substrate, which can cause latch-up, permanently brick the silicon, or inject noise into adjacent channels on a multiplexed chip. Always use clamping diodes or a precision op-amp limiter on the front end if overvoltage is possible.
Why does my 16-bit SAR ADC only give me 12 bits of effective resolution?
This is dictated by the Effective Number of Bits (ENOB). A 16-bit SAR ADC has a theoretical Signal-to-Noise and Distortion Ratio (SINAD) of 98 dB. However, internal thermal noise, reference voltage noise, and harmonic distortion from the input driver degrade this figure. If your system's total noise floor is 74 dB, your ENOB drops to 12 bits. To reclaim your 16-bit resolution, you must lower the noise floor by using a low-noise linear regulator for V_REF, implementing a proper 4-layer PCB ground plane, and oversampling the signal in software to average out broadband thermal noise.
