An SR (Set-Reset) latch is the most basic bistable sequential logic circuit that stores a single bit of data by cross-coupling two logic gates to maintain one of two stable output states until explicitly changed. In a real circuit or installation, it changes how we handle transient signals by converting a messy, momentary physical event—like a button press or a limit switch trip—into a clean, persistent logic state that a microcontroller or relay can reliably read. Think of it like a mechanical door latch: once you push the handle down (Set), the door stays open even after you remove your hand, and it only closes when you explicitly turn the knob back up (Reset).
While modern microcontrollers can handle a lot of logic in software, discrete SR latches remain critical for hardware-level interlocks, power-on sequencing, and capturing nanosecond-scale fault events that a CPU polling loop would miss. Below, we break down the logic, look at real silicon specifications, and walk through a numeric design example.
The SR Latch Truth Table and Real-World IC Specs
Most practical SR latches you will buy off the shelf are built using cross-coupled NAND gates. Because of the NAND logic, the inputs are active-LOW, typically labeled $\overline{S}$ and $\overline{R}$. When both inputs are HIGH (inactive), the latch holds its previous state. Pulling $\overline{S}$ LOW forces the Q output HIGH; pulling $\overline{R}$ LOW forces Q LOW.
Logic Truth Table (Active-LOW NAND Implementation)
| $\overline{S}$ (Set) | $\overline{R}$ (Reset) | Q (Output) | $\overline{Q}$ (Inverted) | State Description |
|---|---|---|---|---|
| HIGH | HIGH | Hold | Hold | No change (Memory state) |
| LOW | HIGH | HIGH | LOW | Set (Output forced to 1) |
| HIGH | LOW | LOW | HIGH | Reset (Output forced to 0) |
| LOW | LOW | HIGH | HIGH | Invalid (Avoid this state) |
Silicon Specifications: 74HC279 vs. CD4043
When designing a board, you aren't just wiring abstract gates; you are selecting a specific IC. Here is how two common quad SR latch families compare at a standard 5V supply.
| Parameter | TI SN74HC279 (High-Speed CMOS) | Nexperia HEF4043B (Standard CMOS) |
|---|---|---|
| Operating Voltage (VCC) | 2.0V to 6.0V | 3.0V to 15.0V |
| Propagation Delay ($t_{pd}$) @ 5V | 14 ns (typical) | 30 ns (typical) |
| Max Output Current ($I_{OH}/I_{OL}$) | ±5.2 mA | ±2.5 mA (varies with VCC) |
| Quiescent Current ($I_{CC}$) | 8 µA (max) | 5 µA (max) |
| Input Logic Thresholds | TTL-compatible (HC series) | Standard CMOS (proportional to VCC) |
Source: Texas Instruments SN74HC279 Datasheet
Worked Numeric Example: Debouncing a Mechanical Switch
The most common bench application for an SR latch is debouncing a mechanical SPDT (Single Pole, Double Throw) switch. When a physical switch contact closes, the metal reed bounces, creating a rapid series of make-and-break pulses that can last anywhere from 1ms to 5ms. If you feed this directly into a microcontroller interrupt, one button press might register as a dozen.
The RC Filter Approach (and why it fails)
A common amateur approach is to use an RC low-pass filter followed by a Schmitt trigger. Let's say we use a 10kΩ resistor and a 100nF capacitor.
- Time Constant ($\tau$): $\tau = R \times C = 10,000 \times 0.0000001 = 1\text{ ms}$.
- Settling Time: To reach 99% of VCC, the capacitor needs $5\tau$, which is 5ms.
During that 5ms window, the voltage ramps slowly. If the switch bounce is severe enough to pull the voltage back down across the Schmitt trigger's hysteresis threshold, you still get multiple edges. Furthermore, you've introduced a 5ms latency into your circuit.
The SR Latch Approach
Instead, we wire the SPDT switch between the $\overline{S}$ and $\overline{R}$ inputs of a 74HC279. The common pole of the switch goes to GND, and both $\overline{S}$ and $\overline{R}$ are pulled up to 5V via 10kΩ resistors.
- Initial Press: The switch throws to the $\overline{S}$ pin, pulling it LOW. The latch propagates this to the Q output in 14 ns ($t_{pd}$ of the 74HC279).
- The Bounce Phase: The switch contact bounces off the $\overline{S}$ pin, letting it float HIGH for a few microseconds, then slams back into the $\overline{S}$ pin. Because the latch is already in the SET state, a subsequent LOW pulse on $\overline{S}$ does absolutely nothing. The output remains rock-solid HIGH.
- The Transfer: The switch throws to the $\overline{R}$ pin. Even if it bounces on the $\overline{R}$ pin for 3ms, the latch only registers the first 14ns edge. Once Q goes LOW, subsequent bounces on $\overline{R}$ are ignored.
Where You Meet This in Practice (and What People Confuse It With)
Beyond switch debouncing, SR latches show up in several critical hardware-level applications where software is too slow or unreliable.
- First-to-Fault Alarm Circuits: In industrial motor control panels, multiple fault sensors (over-temp, over-current, phase loss) might trip simultaneously. By wiring each sensor to a separate SR latch in a quad IC, the very first fault to trip (even by nanoseconds) sets its latch and disables the others, locking in the "first cause" for the technician to read on an LED display.
- Crowbar Interlocks: In high-voltage power supplies, if the output exceeds a safe threshold, a comparator triggers an SCR to short the output and blow the fuse. An SR latch is often used to hold the trigger signal HIGH to ensure the SCR fires completely, even if the over-voltage condition instantly collapses and the comparator resets.
- Power-On Sequencing: Latches are used to enforce strict power-up orders. Rail B cannot be enabled until the Power-Good signal from Rail A sets the latch that enables Rail B's regulator.
Common Confusion: SR Latch vs. SR Flip-Flop
Beginners frequently confuse latches with flip-flops, using the terms interchangeably. In strict digital design theory, they are distinct:
- SR Latch: Level-sensitive (or asynchronous). The output changes immediately when the S or R input changes state. There is no clock signal. It is transparent to the inputs as long as they are active.
- SR Flip-Flop: Edge-triggered (or synchronous). The S and R inputs are only sampled at the exact moment a clock signal transitions (e.g., the rising edge). If S is HIGH but the clock isn't ticking, the output ignores it.
If you need to synchronize a physical event to a system clock, you use a flip-flop. If you need to capture an event the exact nanosecond it happens and hold it indefinitely, you use a latch.
Frequently Asked Questions
Can I build an SR latch from discrete transistors?
Yes, you can build one using two NPN transistors (like the 2N3904) cross-coupled with base resistors. However, discrete implementations suffer from asymmetric propagation delays and temperature drift. For $0.15, a 74HC279 gives you four perfectly matched latches in a single SOIC package with guaranteed nanosecond timing.
What happens if I leave the inputs floating?
CMOS inputs (like the 4000 series or 74HC series) have extremely high impedance. A floating input will pick up ambient electromagnetic noise, causing the latch to randomly toggle and overheat the IC due to rapid internal switching currents. Always use pull-up or pull-down resistors (typically 10kΩ) on unused or switch-driven inputs.
How do I reset the latch on power-up?
Standard SR latches power up in an undefined state. If you need a known state at boot, use an IC with an asynchronous Master Reset pin (like the CD4043), or wire a simple RC delay (10kΩ and 1µF) to the $\overline{R}$ input to force a LOW pulse the moment VCC rises.
