When studying circuit theory, a textbook example of voltage calculation often assumes ideal components and infinite load impedances. In the real world, connecting a microcontroller's Analog-to-Digital Converter (ADC) to a voltage divider introduces a parallel load that drags the node voltage down. If you ignore this loading effect, your firmware will read incorrect sensor data, leading to flawed control logic or inaccurate telemetry. This walkthrough breaks down a classic exam-style problem that bridges theoretical Ohm's law with practical embedded systems design.
The Core Problem: Finding the True Example of Voltage in a Loaded Divider
A 12.0V DC power supply feeds a voltage divider consisting of $R_1 = 10k\Omega$ (top) and $R_2 = 10k\Omega$ (bottom, tied to ground). A microcontroller ADC with an input impedance ($R_{load}$) of $100k\Omega$ is connected in parallel across $R_2$. Calculate the exact voltage at the ADC pin ($V_{out}$). Identify the method used, show all algebraic steps, and determine the percentage of error introduced if the load impedance is ignored.
Before solving, it is crucial to understand how different ADC architectures impact this exact scenario. The internal sample-and-hold capacitors and multiplexers of various chips present wildly different input impedances. Below is a data-dense reference table showing how this specific 10k/10k divider behaves when loaded by common 2026-era microcontrollers and external ADCs.
| Microcontroller / ADC IC | Typical Input Impedance | Ideal Divider $V_{out}$ | Actual Loaded $V_{out}$ | Measurement Error |
|---|---|---|---|---|
| ATmega328P (Arduino Uno R3) | ~100 MΩ (with MUX) | 6.000 V | 5.999 V | -0.01% |
| ESP32-S3 (Internal ADC) | ~10 kΩ to 100 kΩ (non-linear) | 6.000 V | ~4.800 V | -20.0% |
| STM32F407 (Internal ADC) | ~50 kΩ (varies with sample time) | 6.000 V | 5.454 V | -9.1% |
| TI ADS1115 (External I2C) | ~710 kΩ (Programmable Gain) | 6.000 V | 5.917 V | -1.3% |
Step-by-Step Algebraic Solution & The Common Trap
Which theorem applies and why?
While you could use Nodal Analysis (Kirchhoff's Current Law) at the $V_{out}$ node, Thevenin's Theorem is the most elegant and computationally efficient method here. Thevenin's theorem allows us to collapse the entire source network ($V_{in}$, $R_1$, and $R_2$) into a single ideal voltage source ($V_{th}$) in series with a single equivalent resistance ($R_{th}$). Once reduced, calculating the loaded voltage becomes a trivial single-step voltage divider calculation.
Step 1: Calculate the Thevenin Equivalent Voltage ($V_{th}$)
Remove the load resistor ($R_{load}$) to find the open-circuit voltage across the terminals.
$$V_{th} = V_{in} \times \left( \frac{R_2}{R_1 + R_2} \right)$$
$$V_{th} = 12.0V \times \left( \frac{10,000\Omega}{10,000\Omega + 10,000\Omega} \right)$$
$$V_{th} = 12.0V \times 0.5 = \mathbf{6.0V}$$
Step 2: Calculate the Thevenin Equivalent Resistance ($R_{th}$)
Short the independent voltage source ($V_{in}$ to ground) and look back into the terminals. $R_1$ and $R_2$ are now in parallel.
$$R_{th} = \frac{R_1 \times R_2}{R_1 + R_2}$$
$$R_{th} = \frac{10,000 \times 10,000}{10,000 + 10,000} = \frac{100,000,000}{20,000} = \mathbf{5,000\Omega} \text{ (or } 5k\Omega)$$
Step 3: Reattach the Load and Solve for $V_{out}$
Now, the circuit is a simple series loop: $V_{th}$ (6.0V) in series with $R_{th}$ ($5k\Omega$) and $R_{load}$ ($100k\Omega$). Apply the voltage divider formula to find the voltage across the load.
$$V_{out} = V_{th} \times \left( \frac{R_{load}}{R_{th} + R_{load}} \right)$$
$$V_{out} = 6.0V \times \left( \frac{100,000}{5,000 + 100,000} \right)$$
$$V_{out} = 6.0V \times \left( \frac{100,000}{105,000} \right)$$
$$V_{out} = 6.0V \times 0.95238... = \mathbf{5.714V}$$
Step 4: Calculate the Loading Error
$$\text{Error} = \left( \frac{5.714V - 6.000V}{6.000V} \right) \times 100 = \mathbf{-4.76\%}$$
A nearly 5% error is massive in precision instrumentation and would easily consume 48 discrete counts on a 10-bit ADC.
Sanity Checks, Independent Verification, and FAQ
Answer Sanity Check:
Let's verify the order of magnitude and physical logic. The ideal unloaded voltage is 6.0V. Adding a parallel load to the bottom resistor must decrease the total resistance of the bottom leg, which in turn must decrease the voltage drop across it. Therefore, our answer must be strictly less than 6.0V. The calculated 5.714V fits this physical requirement. The units are strictly in Volts (V), and the magnitude is reasonable given that the load ($100k\Omega$) is 20 times larger than the Thevenin resistance ($5k\Omega$), meaning the loading effect should be relatively small (roughly $1/20$ or $5\%$, which aligns perfectly with our 4.76% error calculation).
How to Verify the Answer Independently:
Do not trust the math until you verify it on the bench or in simulation.
1. Simulation: Draft the schematic in LTspice. Place a 12V DC source, two 10k resistors, and a 100k load resistor. Run an `.op` (operating point) simulation. The node voltage will read exactly 5.71428V.
2. Physical Measurement: Build the circuit using 1% tolerance metal film resistors. Measure the output using a high-impedance digital multimeter (DMM) like a Fluke 87V, which boasts a 10 MΩ input impedance. Note that the DMM itself acts as a parallel load, but at 10 MΩ, its drag on a 5kΩ Thevenin source is mathematically negligible ($<0.05\%$ error).
Frequently Asked Questions
Q: What if my power supply has internal resistance?
A: You simply add the power supply's internal resistance ($R_{source}$) to $R_1$ before starting the Thevenin reduction. If the supply has $50\Omega$ of internal resistance, treat $R_1$ as $10,050\Omega$ in Step 1 and Step 2.
Q: Can I just use lower value resistors (e.g., 1kΩ and 1kΩ) to eliminate the loading error?
A: Lowering the divider impedance reduces the Thevenin resistance ($R_{th}$ becomes $500\Omega$), which virtually eliminates the 100kΩ loading error. However, this increases the continuous current draw from 0.6 mA to 6 mA, wasting power and generating excess heat. In battery-operated IoT devices, keeping high-value resistors and buffering with an op-amp is the superior engineering choice.
