A series RLC circuit places a resistor, inductor, and capacitor in a single continuous current loop. At its resonant frequency, the inductive and capacitive reactances cancel out, leaving only the resistance to limit current. For low-impedance voltage sources (like a 50-ohm function generator or an op-amp output), the series RLC is the default topology over a parallel tank circuit because it provides minimum impedance at resonance, making it ideal for bandpass, lowpass, highpass, and notch filtering without requiring a high-impedance current drive.

The Series RLC Topology and Node Map

To design or troubleshoot effectively, you must define your nodes. In a standard series bandpass configuration, the components are arranged sequentially from the source to ground:

  • Node 0 (Vin): AC voltage source input.
  • Node 1: Junction between the source and the Resistor (R).
  • Node 2: Junction between the Resistor (R) and the Inductor (L).
  • Node 3 (Vout): Junction between the Inductor (L) and the Capacitor (C). Note: For a bandpass filter, Vout is typically taken across the resistor, meaning Vout is between Node 1 and Node 2, or the component order is rearranged so R is at the bottom.
  • Node 4 (GND): Ground return.
Why Series Over Parallel?
A parallel RLC circuit exhibits maximum impedance at resonance and requires a high-impedance current source (or a voltage source with a massive series resistor) to achieve a high Q-factor. If you drive a parallel tank with a low-impedance 50-ohm lab source, the source impedance swamps the tank, flattening the resonance peak entirely. The series RLC exhibits minimum impedance at resonance, perfectly matching low-impedance voltage sources. According to All About Circuits, series resonance is the standard for voltage-driven bandpass applications.

Component Behavior and Resonance Mechanics

The resonant frequency ($f_r$) is dictated strictly by L and C: $f_r = 1 / (2\pi\sqrt{LC})$. The Q-factor (quality factor) and bandwidth are controlled by R. Here is how altering one element shifts the circuit's behavior, assuming the other two remain constant:

Parameter Changed Resonant Freq ($f_r$) Q-Factor Bandwidth (-3dB) Impedance at $f_r$
Increase R Unchanged Decreases Increases (wider) Increases
Increase L Decreases Increases Decreases (narrower) Unchanged (equals R)
Increase C Decreases Decreases Increases (wider) Unchanged (equals R)

Design Walkthrough: Building a 10 kHz Bandpass Filter

Let's design a series RLC bandpass filter targeting $f_r = 10 \text{ kHz}$ with a Q-factor of 10. We will select real, purchasable components rather than theoretical ideal values.

Step 1: Select the Inductor (L)
Inductors are harder to source in exact values and suffer from parasitic DC resistance (DCR). We start here. Choose a Bourns 78F-103K-RC (10 mH radial inductor). It costs about $1.20 and has a specified DCR of 1.5 $\Omega$.

Step 2: Calculate the Capacitor (C)
Using $C = 1 / (4\pi^2 f_r^2 L)$:
$C = 1 / (4 \times \pi^2 \times 10,000^2 \times 0.01) = 25.33 \text{ nF}$.
Standard E12 values don't hit 25.33 nF exactly. We will parallel a 22 nF and a 3.3 nF Wima MKP film capacitor to get 25.3 nF. Avoid cheap Y5V ceramics here; their capacitance drops drastically with applied AC voltage.

Step 3: Calculate the Resistor (R)
The formula for Q in a series circuit is $Q = (1/R) \times \sqrt{L/C}$.
Rearranging for R: $R = (1/Q) \times \sqrt{L/C}$.
$R = (1/10) \times \sqrt{0.01 / 25.3 \times 10^{-9}} = 0.1 \times 628.9 = 62.89 \Omega$.
However, our inductor already has 1.5 $\Omega$ of DCR. The intentional resistor must be $62.89 - 1.5 = 61.39 \Omega$. The closest standard 1% metal film value is 61.9 $\Omega$ (Vishay MRS25 series). Place this resistor at the bottom of the chain (Node 3 to GND) and tap Vout across it to create your bandpass response.

Safety Warning: Q-Multiplication
At resonance, the voltage across the inductor and capacitor is Q times the input voltage. If you drive this circuit with 10V RMS, the voltage across the 10 mH inductor will be $10 \times 10 = 100\text{V RMS}$. Ensure your capacitor's voltage rating exceeds this multiplied voltage, and keep your hands clear of the nodes during high-power testing.

Failure Modes: What Breaks at the Extremes?

When debugging a dead board, you need to know how component failures manifest. A single open or short drastically alters the topology.

Component Failure Mode Circuit Result Diagnostic Symptom
Resistor (R) Opens Broken loop Zero output at all frequencies.
Resistor (R) Shorts Pure LC Tank Massive current spike at $f_r$; Q approaches infinity; output drops to zero if Vout was across R.
Inductor (L) Opens Broken loop Zero output at all frequencies.
Inductor (L) Shorts RC Lowpass $f_r$ vanishes; circuit passes low frequencies and rolls off high frequencies.
Capacitor (C) Opens Broken loop Zero output at all frequencies (blocks DC/AC).
Capacitor (C) Shorts RL Highpass $f_r$ vanishes; circuit blocks DC but passes high frequencies directly to ground if R is at the top.

Breadboard Testing and Verification Steps

Simulations (like LTspice) assume ideal ground planes. Breadboards introduce stray capacitance (~2 pF per contact) and inductance. Follow these steps to verify your physical build using a Siglent SDG1032X function generator and a Rigol DS1054Z oscilloscope.

  1. Build the Chain: Insert the Bourns inductor, Wima capacitors, and Vishay resistor in a single line on the breadboard. Keep leads as short as possible to minimize stray inductance.
  2. Connect the Source: Use a BNC-to-alligator cable from the function generator. Connect the center conductor to Node 0 and the ground clip to the ground rail. Do not use the long ground spring on your scope probe; use the short pigtail clip to avoid picking up radiated noise.
  3. Probe Vout: Attach Channel 1 to the function generator output (Vin) and Channel 2 across the 61.9 $\Omega$ resistor (Vout).
  4. Sweep for Resonance: Set the generator to a 1Vpp sine wave. Sweep manually from 1 kHz to 50 kHz. Note the frequency where the Vout amplitude peaks. It should read close to 10 kHz.
  5. Measure Bandwidth: Record the peak Vout voltage. Calculate the -3dB point (Peak $\times 0.707$). Sweep down in frequency to find the lower -3dB point, and sweep up to find the upper -3dB point. The difference between these two frequencies is your bandwidth. For Q=10 at 10 kHz, expect a bandwidth of roughly 1 kHz.

Decision Path: Series vs. Parallel RLC Selection

Use this decision matrix to lock in your topology before opening your CAD software or parts bin. For a deeper look at automated component sizing, the Analog Devices Filter Wizard is an excellent supplementary tool for active and passive networks.

Design Condition Choose Topology Reasoning
Source impedance is low (< 50 $\Omega$) Series RLC Low source Z won't dampen the series resonance peak.
Source impedance is high (> 1 k$\Omega$) Parallel RLC High source Z acts as a current source, allowing parallel tank to ring.
Need a Bandpass filter with low insertion loss Series RLC At $f_r$, series Z is minimal (just R), passing maximum voltage.
Need a Bandstop (Notch) filter Series RLC Take output across the L+C series combination; at $f_r$, their combined Z is near zero, shorting the signal to ground.
Need to block DC but pass a specific AC band Series RLC The series capacitor inherently blocks DC bias from the source.

The Default Recommendation: If you are working in a standard lab environment with 50-ohm equipment, or designing audio line-level filters driven by op-amps (which have < 100-ohm output impedance), default to the Series RLC topology. Specifically, use the configuration outlined in our walkthrough: source -> L -> C -> R(to ground), tapping Vout across the resistor. It provides predictable Q control, inherent DC blocking, and interfaces perfectly with modern low-impedance test gear and driver ICs.