A series RLC AC circuit diagram maps a resistor, inductor, and capacitor in a single continuous loop driven by an alternating voltage source. At resonance, the inductive and capacitive reactances cancel each other out, leaving only the resistance to limit current. This topology is the foundation of RF tuning, audio crossovers, and impedance matching networks. Below is a complete design walkthrough using real component values, failure-mode analysis, and a physical breadboard testing procedure.
Topology and Node Mapping
Before picking parts, we must define the physical nodes. In a standard series RLC bandpass configuration, the components are daisy-chained between the AC source and ground. The output voltage is typically measured across the resistor to observe the bandpass filter effect.
- Node A (Source High): The output terminal of the AC function generator.
- Node B (R-L Junction): The electrical connection between the resistor and the inductor.
- Node C (L-C Junction): The connection between the inductor and the capacitor.
- Node D (Source Low / GND): The ground return path, connecting the capacitor back to the function generator's ground.
Component Selection and Design Walkthrough
Let's design a series RLC circuit tuned to a 5 kHz resonant frequency ($f_r$). We will use standard, off-the-shelf component values rather than theoretical ideals.
1. Select the Capacitor (C):
We need a non-polarized dielectric capable of handling AC voltage swings without distortion. A 100 nF (0.1 µF) X7R ceramic capacitor rated for 50V is ideal. Avoid Y5V dielectrics, as their capacitance drops drastically with applied voltage.
2. Calculate the Inductor (L):
Using the resonance formula $f_r = 1 / (2\pi\sqrt{LC})$, we solve for L:
$L = 1 / ((2\pi \times 5000)^2 \times 100 \times 10^{-9})$
$L \approx 10.13$ mH. We will select a standard 10 mH radial leaded inductor. Note that real inductors have DC resistance (DCR); expect about 2Ω to 5Ω of parasitic series resistance here.
3. Select the Resistor (R):
The resistor sets the Q-factor (quality factor) and the bandwidth. Let's use a 47Ω 1/4W metal film resistor.
$Q = (1 / R_{total}) \times \sqrt{L / C}$
Assuming $R_{total} = 47\Omega + 3\Omega (inductor DCR) = 50\Omega$:
$Q = (1 / 50) \times \sqrt{0.01 / 0.0000001} = 0.02 \times 316.2 = 6.32$
A Q of 6.32 gives a -3dB bandwidth of roughly 790 Hz ($5000 / 6.32$). This is sharp enough to demonstrate a clear peak on an oscilloscope, but wide enough that minor component tolerances won't hide the resonance.
Behavior Matrix and Topology Contrast
Understanding how an AC circuit diagram behaves when pushed to its extremes is critical for troubleshooting. The table below maps component changes and catastrophic failures.
| Element Change / Failure | Effect on Resonant Freq ($f_r$) | Effect on Q-Factor | Extreme Failure Mode (Short/Open) |
|---|---|---|---|
| Increase C | Decreases | Slight increase | Short: $f_r$ shifts to infinity; circuit becomes a simple RL low-pass. Open: Current drops to zero. |
| Increase L | Decreases | Increases (if DCR is low) | Short: $f_r$ shifts to infinity; circuit becomes an RC high-pass. Open: Current drops to zero. |
| Increase R | No change | Decreases (peak flattens) | Short: Current spikes, Q approaches theoretical infinity, inductor/core may overheat. Open: Current drops to zero. |
Why Series RLC Over Parallel RLC?
When reviewing an AC circuit diagram, you must choose between series and parallel topologies based on your source impedance. A series RLC circuit exhibits minimum impedance at resonance. It acts as a bandpass filter for current, making it the correct choice when driven by a low-impedance voltage source like a standard function generator (typically 50Ω output impedance).
Conversely, a parallel RLC (tank) circuit exhibits maximum impedance at resonance. If you drive a parallel tank with a low-impedance voltage source, the source will simply force the voltage across the tank, masking the resonant voltage peak. Parallel topologies require a high-impedance current source to function as a bandpass filter. For bench testing and most signal-routing applications, the series topology is vastly superior and easier to measure.
Step-by-Step Breadboard Testing
Simulating an AC circuit diagram in SPICE is useful, but parasitic elements on a physical breadboard will alter your results. Follow this procedure to test the 5 kHz design.
- Prepare the Layout: Insert the 47Ω resistor, 10 mH inductor, and 100 nF capacitor in a single series row. Keep the inductor at least 1 inch away from the function generator leads to prevent magnetic coupling from inducing ghost voltages.
- Connect the Source: Attach the function generator's BNC-to-alligator clip cable. Connect the center conductor (red) to Node A and the ground clip (black) to Node D. Set the generator to a 10V peak-to-peak (Vpp) sine wave at 1 kHz.
- Probe the Output: Connect your oscilloscope probe (set to 10x attenuation) across the 47Ω resistor (Probe tip to Node B, ground clip to Node D). Never clip the scope ground to Node A or Node B, as this will short out the resistor or inductor through the scope's earth ground.
- Perform the Frequency Sweep: Slowly increase the function generator frequency from 1 kHz to 10 kHz. Watch the oscilloscope's Vpp measurement. You will see the voltage across the resistor rise, peak sharply around 5 kHz, and then fall off.
- Verify the Peak: Fine-tune the frequency in 10 Hz increments around 5000 Hz. Due to the 5% tolerance of the inductor and the breadboard's ~3pF of stray row capacitance, your actual peak will likely land between 4950 Hz and 5100 Hz.
AC Circuit Diagram FAQ
Why does my physical AC circuit diagram resonate at a different frequency than calculated?
Theoretical calculations assume ideal components. In reality, a 10 mH radial inductor has inter-winding parasitic capacitance (often 10pF to 30pF) and a core permeability that shifts slightly with temperature. Furthermore, a standard solderless breadboard introduces roughly 2pF to 5pF of stray capacitance between adjacent rows. These parasitics add to your 100 nF capacitor, slightly lowering the actual resonant frequency. To minimize this, use a PCB or point-to-point perfboard for final validation.
Can I use a polarized electrolytic capacitor in an AC circuit diagram?
No. Electrolytic capacitors rely on a microscopic oxide layer formed by a specific DC voltage polarity. If you place an electrolytic capacitor in a pure AC circuit, the reverse-bias half-cycles will dissolve the dielectric layer, causing massive leakage current, internal heating, and eventual venting or explosion. Always use non-polarized film capacitors (polyester, polypropylene) or X7R/C0G ceramics for AC signal paths.
How do I measure the phase shift in this AC circuit diagram?
At exact resonance, the circuit is purely resistive, meaning the source voltage (Node A) and the resistor voltage (Node B) are perfectly in phase (0° shift). Below resonance, the capacitor dominates, and the current leads the voltage. Above resonance, the inductor dominates, and the current lags. To measure this, connect Oscilloscope Channel 1 to Node A and Channel 2 to Node B. Use the scope's 'Delay' or 'Phase' measurement function, or trigger on Channel 1 and measure the time delta ($\Delta t$) between the zero-crossings. Calculate phase angle using: $\theta = (\Delta t / T) \times 360^\circ$, where T is the signal period.
What happens to the voltage across the inductor and capacitor at resonance?
This is where series resonance becomes dangerous in high-power applications. At resonance, the voltage across the inductor ($V_L$) and the capacitor ($V_C$) are equal in magnitude but 180° out of phase, so they cancel out from the perspective of the source. However, individually, they are amplified by the Q-factor. In our 5 kHz design with a Q of 6.32 and a 10Vpp source, the voltage across the capacitor will be roughly $10V \times 6.32 = 63.2Vpp$. If you had used a 25V-rated capacitor, it would suffer dielectric breakdown despite the source only outputting 10V.
