The series connection of capacitors is a fundamental circuit topology used primarily to increase the overall working voltage DC (WVDC) rating of a capacitor bank while sacrificing total capacitance. If you wire two identical 100µF, 50V capacitors in series, the resulting equivalent capacitance drops to 50µF, but the string can safely withstand 100V. Unlike resistors in series, where resistance adds linearly, series capacitance follows an inverse reciprocal formula, and the voltage divides inversely proportional to the capacitance values. This guide breaks down the exact node topology, real-world leakage imbalances, and step-by-step breadboard verification for series capacitor strings.

Topology, Node Labels, and the Inverse Voltage Rule

To analyze a series capacitor string, we define three primary nodes in a basic two-component circuit:

  • Node A (High/Input): The positive terminal of the first capacitor (C1), connected to the voltage source.
  • Node B (Midpoint/Junction): The electrical connection between the negative terminal of C1 and the positive terminal of C2. In a DC circuit, this node is floating; in an AC circuit, it serves as the tap for a capacitive voltage divider.
  • Node C (Low/Ground): The negative terminal of the second capacitor (C2), connected to the return path or ground.

Because the components share a single continuous path, the charge (Q) stored on each capacitor is identical (Q1 = Q2 = Q_total). Since Q = C × V, the voltage across any individual capacitor is calculated as V_x = Q / C_x. This leads to the critical inverse voltage division rule: the smallest capacitor in a series string drops the largest share of the voltage. For a detailed mathematical breakdown of this principle, the All About Circuits DC textbook chapter on series capacitors provides an excellent foundational proof.

Bench Rule of Thumb: If you are mixing capacitance values in series (e.g., a 10µF and a 40µF cap), the 10µF cap will absorb 80% of the total applied voltage. Always verify the WVDC of the smallest capacitor first.

Real-World Design: 400V DC Bus Filter With Balancing

Theory assumes ideal components, but real-world electrolytic capacitors have significant leakage current tolerances. If you place two 450V capacitors in series across a 400V DC bus, the theoretical voltage split is 200V each. However, if C1 has a leakage current of 0.2mA and C2 has a leakage of 0.8mA, C1 acts as a higher impedance than C2. The voltage will divide based on leakage resistance, not capacitance. C1 could see 320V while C2 sees 80V. Over time, C1 exceeds its rated voltage, its dielectric breaks down, and it vents or explodes.

To fix this, we use balancing (bleeder) resistors in parallel with each capacitor. These resistors are sized to draw a current significantly higher than the worst-case leakage current, forcing the voltage to divide evenly based on the resistor ratio rather than the capacitor leakage.

Below is the spec sheet for a 400V DC link filter designed for a variable frequency drive (VFD) or solar inverter application, requiring roughly 100µF of bulk capacitance.

Table 1: 400V DC Bus Series Capacitor Design Specifications
Parameter Component 1 (C1) Component 2 (C2) Combined Series String
Part Number Nichicon LGU2W221MELB Nichicon LGU2W221MELB N/A
Nominal Capacitance 220µF 220µF 110µF
WVDC Rating 450V 450V 900V (Theoretical)
Max Leakage Current (Datasheet) 2.97mA 2.97mA N/A
Balancing Resistor Vishay 220kΩ 2W Metal Film Vishay 220kΩ 2W Metal Film 440kΩ Total Bleed Path
Steady-State Voltage (at 400V DC) 200V ± 2% 200V ± 2% 400V DC

By using 220kΩ resistors, the bleed current through each resistor is approximately 0.9mA (200V / 220kΩ). This external current path is substantial enough to swamp minor leakage mismatches between the two capacitors, ensuring Node B sits firmly at half the bus voltage. For more on managing electrolytic leakage in high-voltage strings, refer to the Electronics Tutorials guide on series capacitors.

Series vs. Parallel and Extreme Failure Modes

Choosing between series and parallel topologies depends entirely on whether your design is constrained by voltage limits or energy storage (capacitance) limits. Here is how the two configurations contrast in practice.

Table 2: Series vs. Parallel Capacitor Topologies
Criteria Series Connection Parallel Connection
Primary Goal Increase WVDC (Voltage Rating) Increase Total Capacitance / Energy Storage
Equivalent Capacitance Decreases (C_eq < smallest C) Increases (C_eq = C1 + C2 + ...)
ESR / ESL Impact Adds linearly (worse high-frequency response) Divides (better high-frequency ripple filtering)
Required Ancillary Parts Balancing resistors mandatory for electrolytics None (though fusing is recommended for large banks)

Fault Behavior Matrix: What Breaks at the Extremes?

When designing protection circuits, you must understand how the string behaves when a single element fails. Below is the behavior table detailing what changes when one element shifts state.

Table 3: Series String Fault Behavior Matrix
Fault Condition on C1 Effect on Total C_eq Effect on Node B Voltage System Consequence
C1 Shorts Becomes equal to C2 Shifts to Node A potential (400V) C2 absorbs 100% of bus voltage. If WVDC < 400V, C2 experiences overvoltage and cascading catastrophic failure (venting/explosion).
C1 Opens Drops to 0µF Floats to undefined / leakage-dependent DC current flow stops entirely. Filter loses all bulk capacitance, causing massive voltage ripple on the DC bus and likely tripping downstream inverter faults.
C1 Leakage Spikes Remains nominally 110µF Drops toward Node C (Ground) Without balancing resistors, C2 absorbs excess voltage. With balancing resistors, the resistors dissipate excess heat, potentially exceeding their 2W power rating.

Step-by-Step Breadboard Verification

Before soldering a series string into a high-voltage PCB or chassis, verify the topology and balancing network on the bench using low-voltage DC. This ensures your midpoint voltage is stable and your equivalent capacitance matches calculations.

SAFETY WARNING: Never test series capacitor strings with high-voltage DC on a breadboard. Breadboard contacts are rated for low voltage (typically < 60V) and low current. High-voltage arcing across breadboard traces can cause severe shock or fire. Use the 12V DC method below for bench verification.
  1. Discharge and Prep: Short the leads of both capacitors with a 1kΩ power resistor to ensure they are fully discharged. Insert C1 and C2 into the breadboard, leaving a gap between the negative lead of C1 and positive lead of C2.
  2. Install Balancing Resistors: Insert the 220kΩ resistors so that each bridges the positive and negative leads of its respective capacitor. Ensure solid contact in the breadboard terminals.
  3. Bridge Node B: Use a short jumper wire to connect the negative lead of C1 to the positive lead of C2. This establishes Node B.
  4. Measure Equivalent Capacitance: Set your digital multimeter (DMM) to capacitance mode. Place the probes across Node A and Node C. The meter should read approximately half the nominal value of a single capacitor (e.g., ~110µF for two 220µF caps). Allow up to 30 seconds for the DMM to charge the caps and settle on a reading.
  5. Apply Low-Voltage DC: Connect a 12V DC bench power supply across Node A (positive) and Node C (negative). Limit the current to 50mA to prevent inrush spikes.
  6. Verify Node B Division: Switch your DMM to DC Voltage mode. Place the black probe on Node C and the red probe on Node B. The reading should be exactly 6.0V DC (half of 12V). If it reads 5.9V or 6.1V, your balancing resistors are successfully swamping minor leakage differences. If it reads 9V or 3V, a resistor is unseated or the wrong value.
  7. Discharge Post-Test: Turn off the power supply and use your 1kΩ discharge resistor across Node A and Node C before touching the circuit.

By following this verification sequence, you confirm both the physical series topology and the efficacy of the balancing network. Once verified, the exact same resistor ratios and component selections can be scaled up for high-voltage PCB layout, ensuring long-term reliability and preventing dielectric breakdown in your final power electronics design.