The Series Capacitor Equation: Why Stack Instead of Buy?

The direct answer for two components is straightforward: the series capacitor equation is calculated as C_eq = (C1 × C2) / (C1 + C2). For N identical capacitors in series, the equivalent capacitance drops to C_eq = C / N, while the theoretical voltage rating multiplies by N.

Why would you intentionally reduce your capacitance and complicate your bill of materials? In practical circuit design, you rarely put capacitors in series just to achieve a smaller capacitance value—you would simply buy a smaller capacitor. The primary engineering driver for series topologies is voltage rating stacking. When designing input filters for off-grid inverters, BLDC motor drivers, or PFC (Power Factor Correction) stages, you frequently encounter DC bus voltages (e.g., 400V to 600V) that exceed the maximum working voltage of readily available, cost-effective, high-quality film capacitors. By stacking components, you divide the voltage stress across multiple dielectrics.

However, treating the series capacitor equation as a pure math exercise will result in catastrophic field failures. Real-world capacitors have leakage currents and equivalent series resistance (ESR) mismatches that destroy theoretical voltage division. This guide walks through the physical topology, the mandatory balancing network, and the exact failure modes you must design around.

Topology & Node Behavior: What Happens When Values Shift

Consider a basic two-capacitor series network acting as a DC bus filter and capacitive voltage divider. We define three critical nodes:

  • Node A (V_IN): The high-voltage DC bus input (e.g., 400V).
  • Node B (V_MID): The midpoint junction between C1 and C2.
  • Node C (GND): The system ground reference (0V).

In a perfect theoretical world with identical capacitors, Node B sits exactly at 50% of V_IN. In reality, capacitance tolerance (typically ±10% for film caps) and leakage current divergence shift this midpoint. Here is how the network behaves when individual elements drift:

Series Network Behavior Matrix
Element ChangeEffect on C_eqEffect on Node B (V_MID)Physical Consequence
C1 increases (e.g., +10% tol)Increases slightlyV_MID drops (Node B moves closer to GND)C2 absorbs a higher share of the total DC voltage.
C1 leakage increasesNo change to AC C_eqV_MID rises toward V_INC1 acts as a lower DC impedance; C2 faces overvoltage and potential dielectric breakdown.
C2 decreases (e.g., aging/drying)DecreasesV_MID rises toward V_INC2's capacitive reactance increases, shifting AC ripple voltage stress onto C2.
Bench Insight: According to foundational circuit theory documented by All About Circuits, series capacitance behaves inversely to series resistance. While series resistors divide voltage proportionally to their resistance, series capacitors divide AC voltage inversely proportional to their capacitance. For DC steady-state, however, voltage division is dictated entirely by leakage resistance, which is why passive balancing resistors are non-negotiable.

Design Walkthrough: 400V DC Bus Filter with 250V Film Caps

Let’s design a real network. You are building a 400V DC bus snubber/filter for a motor controller. You need roughly 2.2µF of bulk capacitance, but high-voltage 500V+ film capacitors are physically massive and cost upwards of $15 each. Standard 250VDC metallized polypropylene film capacitors (like the KEMET R75 series or WIMA MKP10) are abundant and cost under $2 each.

Step 1: Sizing the Capacitors

We need ~2.2µF. Using the series capacitor equation for two identical caps: C = C_eq × 2.
Target C = 2.2µF × 2 = 4.4µF.
We select two 4.7µF, 250VDC WIMA MKP10 film capacitors.
Resulting C_eq = 2.35µF (well within standard tolerance for a snubber).
Theoretical voltage rating = 250V + 250V = 500V, providing a safe 20% derating margin for a 400V bus.

Step 2: Sizing the Balancing (Bleeder) Resistors

This is where most hobbyist designs fail. If C1 has a slightly higher leakage current than C2, C1's effective DC resistance drops. Node B will drift upward, and C2 will see 280V or 300V, exceeding its 250V rating and eventually shorting. To force a 50/50 DC voltage split, we place high-value resistors in parallel with each capacitor.

The Math: The current flowing through the balancing resistors must be at least 10 times the worst-case leakage current of the capacitors. Polypropylene film caps have exceptionally low leakage (typically < 0.1µA per µF). For a 4.7µF cap, leakage is < 0.5µA. We want at least 5µA flowing through our resistors.

At 200V per resistor: R = V / I = 200V / 5µA = 40MΩ.
To be conservative and ensure rapid discharge when power is removed, we select 10MΩ resistors. This draws 20µA, easily dominating the capacitor leakage.

The Expert Catch (Resistor Voltage Rating): Do not just check the power rating. Power dissipation is tiny (P = V²/R = 200² / 10,000,000 = 4mW). A 1/4W resistor handles the heat easily. However, standard 1/4W resistors have a maximum working voltage of roughly 250V. If Node B shifts transiently, a 1/4W resistor might arc internally. Always use 1/2W or 1W metal film resistors (rated for 350V–500V working voltage) for HV DC balancing networks.

Failure Modes at the Extremes

Why choose series over parallel? Parallel topologies increase capacitance and current-handling capability, but the voltage rating remains limited to the lowest-rated component in the bank. Series topologies sacrifice capacitance to multiply voltage handling. But this comes with distinct failure modes that you must protect against.

  • Extreme 1: C1 Shorts. If C1 suffers a dielectric breakdown and shorts, Node A (400V) is instantly connected to Node B. C2 now absorbs the entire 400V bus. Because C2 is only rated for 250V, it will undergo catastrophic avalanche failure, likely venting plasma or exploding. Mitigation: Use film capacitors (which tend to fail open or clear the short internally via self-healing metallization) rather than electrolytics, and ensure upstream fusing is correctly sized.
  • Extreme 2: C1 Opens. If a lead breaks or an internal connection fails open, the series circuit is broken. C_eq drops to effectively zero. The DC bus loses its high-frequency snubber filtering, leading to voltage spikes that may destroy downstream MOSFETs or IGBTs. Mitigation: Implement bus overvoltage monitoring via a microcontroller ADC.
  • Extreme 3: Balancing Resistor Opens. If the 10MΩ resistor across C1 fails open, the DC voltage division reverts to the natural leakage mismatch of the capacitors. Node B will slowly drift over minutes or hours until one capacitor exceeds its voltage rating. Mitigation: Use high-reliability metal film resistors and inspect solder joints during manufacturing.

Scaled Bench Testing: Proving the Midpoint

SAFETY WARNING: Never prototype or test 400V DC circuits on a standard solderless breadboard. The contact resistance is unpredictable, and the risk of lethal shock or arc flash is severe. To verify the series capacitor equation and the necessity of balancing resistors, we scale the test down to safe bench voltages.

Warning: De-energize and verify all circuits with a tested multimeter before touching nodes. For high-voltage final implementations, local electrical codes and safety standards require proper enclosure, creepage/clearance distances on the PCB, and potentially review by a licensed professional.

We will use two 10µF, 50V aluminum electrolytic capacitors and a 24V DC bench supply. Electrolytics have notoriously high and mismatched leakage currents, making them perfect to demonstrate the balancing problem.

  1. Build the Unbalanced Circuit: Insert C1 and C2 in series on the breadboard. Connect the positive rail to 24V and the negative rail to GND.
  2. Measure V_MID: Use your multimeter to measure the voltage at the junction between C1 and C2. You will likely read something highly asymmetrical, like 16V on one and 8V on the other, due to random leakage mismatches from the factory.
  3. Add Balancing Resistors: Power down the supply. Place two 100kΩ resistors in parallel with C1 and C2 respectively. (At 12V, 100kΩ draws 120µA, easily overpowering the electrolytic leakage).
  4. Re-measure V_MID: Power the supply back on. The midpoint voltage will now snap tightly to 12.0V (±0.1V), proving that the parallel resistive network successfully overrides the capacitive leakage mismatch and enforces the theoretical 50/50 split dictated by your design.

For deeper theoretical background on how dielectric absorption and leakage impact series networks, refer to the capacitor series tutorials at Electronics Tutorials.

Decision Tree: Topology Selection & Default Picks

Use this decision matrix to determine whether your application requires a series, parallel, or single-component topology.

Topology Decision Matrix
Design ConstraintParallel TopologySingle ComponentSeries Topology
Need higher capacitance, voltage is lowYESOnly if physically availableNO (Reduces capacitance)
Need higher voltage handling, capacitance is flexibleNO (Voltage limited by lowest part)Only if HV parts are in budget/stockYES
Need high ripple current handlingYES (Current divides)Depends on partNO (Current is identical through all)
Board space is highly constrainedNO (Multiple footprints)YESNO (Multiple footprints + resistors)

The Default Recommendation

If your DC bus voltage exceeds 80% of the rated voltage of your preferred capacitor family (e.g., you have a 400V bus and want to use standard 400V or 450V electrolytics), do not rely on a single component. Derating is critical for longevity.

Concrete Pick: For DC bus filtering between 300V and 600V, default to a series topology using two 250VDC or 310VDC metallized polypropylene film capacitors (e.g., KEMET R75 or EPCOS/TDK B32620 series), paired with 1/2W 10MΩ metal film balancing resistors. This configuration guarantees self-healing dielectric behavior, avoids the catastrophic venting associated with over-stressed electrolytics, and ensures a stable, predictable midpoint voltage over the lifespan of the equipment.