A field effect transistor (FET) controls current flow using an electric field rather than base current, giving it near-infinite input impedance and making it the undisputed king of modern switching and amplification. Unlike BJTs that require continuous base current to stay on, a FET only requires voltage at the Gate to establish a conductive channel between the Drain and Source. If you need a default N-channel MOSFET for low-side switching under 50V, buy the IRLZ44N (logic-level 5V/3.3V drive) or the IRF540N (standard 10V drive). For small-signal 3.3V/5V logic translation under 200mA, the 2N7000 is the bench standard.

Pinout, Symbols, and Safe Default Part Numbers

Every standard field effect transistor features three terminals: the Gate (G) (the control electrode), the Drain (D) (where current enters the channel in an N-channel device), and the Source (S) (where current exits). In schematic symbols, the arrow on the Source pin always points inward for N-channel devices and outward for P-channel devices. For power MOSFETs, the symbol also includes a body diode pointing from Source to Drain (N-channel), which is a parasitic artifact of the silicon manufacturing process but heavily impacts circuit design.

Choosing the right FET prevents thermal runaway and logic-level mismatching. The table below lists the most reliable, widely available default part numbers for general-purpose bench work and DIY power systems.

Table 1: Safe Default Field Effect Transistors for Bench and Prototyping
Part Number Type / Channel Vds (Max) Id (Continuous) Rds(on) @ Vgs Vgs(th) Package
2N7000 MOSFET / N-Ch 60V 200mA 1.2Ω @ 10V 0.8V - 3.0V TO-92
IRLZ44N MOSFET / N-Ch 55V 47A 0.022Ω @ 5V 1.0V - 2.0V TO-220
IRF540N MOSFET / N-Ch 100V 33A 0.044Ω @ 10V 2.0V - 4.0V TO-220
IRF9540 MOSFET / P-Ch -100V -23A 0.117Ω @ -10V -2.0V to -4.0V TO-220
J310 JFET / N-Ch 25V 40mA N/A (Vgs(off)) -2.0V to -6.0V TO-92
Bench Tip: Notice the "L" in IRLZ44N. That denotes a Logic-Level gate threshold. Standard MOSFETs like the IRF540N require 10V on the Gate to achieve their rated Rds(on). If you drive an IRF540N directly from an ESP32 (3.3V) or Arduino (5V), it will only partially turn on, acting as a resistor and burning up under load. Always use "L" series or logic-level FETs for microcontroller projects.

Operation Regions and Biasing for the Job

Biasing a field effect transistor correctly requires understanding its three distinct operating regions. A massive point of confusion for hobbyists transitioning from BJTs is the terminology: what BJT designers call "saturation" (the fully-ON switch state), MOSFET designers call the "Ohmic" or "Triode" region. In MOSFET physics, "Saturation" actually refers to the constant-current amplification region. According to the All About Circuits Semiconductor Textbook, mixing these terms up is the leading cause of blown switching circuits.

Table 2: FET Operation Regions and Biasing Conditions (N-Channel)
Region Name Bias Condition Behavior Primary Use Case
Cutoff Vgs < Vgs(th) Channel is pinched off. Id = 0 (ignoring micro-amp leakage). Switch OFF state.
Ohmic (Linear/Triode) Vgs > Vgs(th) AND Vds < (Vgs - Vgs(th)) Channel is fully enhanced. Acts as a low-value resistor (Rds(on)). Switch ON state, PWM motor control, power routing.
Saturation (Active) Vgs > Vgs(th) AND Vds > (Vgs - Vgs(th)) Channel is pinched off at the Drain end. Id is constant and controlled only by Vgs. Linear amplifiers, constant current sources, audio preamps.

How to select Vgs for switching: Never design a switch based on Vgs(th) (Gate-Source Threshold Voltage). Vgs(th) is merely the voltage where the FET begins to conduct (usually defined at a tiny 250µA test current). To achieve the low Rds(on) listed in the datasheet, you must drive the Gate to the voltage specified in the Rds(on) test conditions—typically 4.5V for logic-level FETs and 10V for standard FETs.

Complete Application Circuit: 12V PWM Motor Driver

Let us apply this theory to a practical, high-reliability circuit. This low-side PWM motor driver uses an ESP32 (3.3V logic) to control a 12V DC motor drawing up to 5A, utilizing the logic-level IRLZ44N.

Component List and Values

  • Q1: IRLZ44N N-Channel MOSFET
  • R1 (Gate Series): 100Ω (1/4W) — Limits peak charging current into the Gate capacitance, preventing ESP32 GPIO brownouts and dampening high-frequency LC ringing.
  • R2 (Gate Pulldown): 10kΩ (1/4W) — Bleeds Gate charge to Ground. Critical for preventing the motor from spinning wildly during microcontroller boot-up when GPIO pins are high-impedance.
  • D1 (Flyback): 1N5819 Schottky Diode — Placed in reverse parallel across the motor terminals (Cathode to 12V, Anode to Drain). Clamps inductive kickback voltage spikes that would otherwise punch through the MOSFET's Drain-Source oxide.
  • U1: ESP32 DevKit V1 (Pin 13 configured for LEDC PWM at 1kHz).

Wiring Sequence

  1. Connect the 10kΩ pulldown resistor (R2) directly between the IRLZ44N Gate and Source pins. Keep the leads as short as possible.
  2. Connect the 100Ω series resistor (R1) between ESP32 GPIO 13 and the MOSFET Gate.
  3. Wire the MOSFET Source pin directly to the system Ground plane.
  4. Wire the MOSFET Drain pin to the negative terminal of the 12V DC motor.
  5. Connect the positive terminal of the 12V DC motor to the 12V power supply positive rail.
  6. Solder the 1N5819 Schottky diode directly across the motor terminals, with the silver stripe (cathode) facing the 12V positive rail.
Safety Warning: Never omit the flyback diode when switching inductive loads (motors, solenoids, relays). When the MOSFET turns off, the collapsing magnetic field generates a voltage spike (V = L * di/dt) that can easily exceed 100V, instantly destroying the 55V-rated IRLZ44N and potentially back-feeding into your microcontroller's ground, frying the CPU.

Failure Modes and Multimeter Diode Testing

Field effect transistors fail in three primary ways: Gate Oxide Punch-Through (applying >20V to the Gate, permanently shorting Gate to Source), Thermal Runaway (insufficient Gate drive causes high Rds(on), generating heat, which paradoxically lowers Vgs(th) and draws more current until the silicon melts), and dv/dt Parasitic Turn-On (fast-switching high-side voltages couple through the Miller capacitance, accidentally turning the FET back on). For detailed gate-drive mitigation strategies, refer to the Texas Instruments Gate Driver Design Guides.

You can diagnose a suspected dead N-channel power MOSFET using a standard Digital Multimeter (DMM) without removing it from the circuit (provided the circuit is fully de-energized and capacitors are discharged).

Step-by-Step DMM Diode Test (N-Channel)

  1. Set the DMM to Diode Test mode. The red probe outputs a small positive voltage (usually 2-3V), and the black probe is the ground reference.
  2. Test the Body Diode (Reverse): Place the Black probe on the Source and the Red probe on the Drain. The meter should read "OL" (Open Loop). This confirms the body diode is reverse-biased and not shorted.
  3. Test the Body Diode (Forward): Place the Red probe on the Source and the Black probe on the Drain. The meter should read a standard silicon diode drop, typically between 0.400V and 0.600V.
  4. Charge the Gate: While keeping the Red probe on the Source, briefly touch the Red probe to the Gate pin as well. This applies positive voltage to the Gate relative to the Source, turning the internal channel ON.
  5. Verify Channel Conduction: Move the Red probe back to the Source (Black probe remains on Drain). The meter should now read near 0.000V or emit a continuity beep. The low-resistance channel has bypassed the body diode.
  6. Discharge and Verify Turn-Off: Touch the Black probe to both the Gate and Source simultaneously to discharge the Gate capacitance. Then, test Red on Source / Black on Drain again. The reading must return to the 0.400V - 0.600V body diode drop. If it stays at 0V, the Gate oxide is punctured and the FET is permanently shorted.

JFET vs. MOSFET: Which Field Effect Transistor Do You Need?

While MOSFETs dominate power switching, the Junction Field Effect Transistor (JFET) remains highly relevant in specific analog applications. Unlike a MOSFET, which has an insulated Gate (Metal-Oxide-Semiconductor), a JFET's Gate is a direct PN junction. This means a JFET is a normally-ON device; you must apply a reverse bias voltage (negative for N-channel) to pinch the channel off.

Table 3: MOSFET vs. JFET Application Matrix
Criterion MOSFET (Enhancement Mode) JFET (Depletion Mode)
Default State (Vgs = 0) OFF (Normally Open) ON (Normally Closed)
Input Impedance Extremely High (>10^12 Ω) High (10^8 to 10^10 Ω)
ESD Sensitivity Very High (Gate oxide easily punctured) Low (Robust PN junction gate)
Best Use Case Digital switching, PWM, power supplies, motor drivers. Low-noise audio preamps, RF mixers, analog switches, constant current diodes.
Typical Default Part IRLZ44N / 2N7000 J310 / 2N5457

When designing audio front-ends or high-impedance sensor buffers where microphonic noise and thermal drift are concerns, reach for a JFET like the 2N5457. For everything else involving microcontrollers, power routing, and digital logic, the enhancement-mode MOSFET is the correct tool for the job. Always verify your Gate drive voltage against the datasheet's Rds(on) test conditions, respect the body diode's orientation, and use a pulldown resistor to keep your system safe during boot sequences.