When you are wiring an ESP32 to a noisy analog sensor or an audio source, the microcontroller’s internal ADC will happily digitize high-frequency switching noise, folding it back into your usable bandwidth as aliasing artifacts. A simple passive RC filter often fails to provide the steep roll-off required without severely attenuating your source signal. The default, decision-forward solution for a sharp -40dB/decade roll-off without loading the source is a unity-gain active Sallen-Key low-pass circuit filter. Below, we will design a 2kHz Butterworth response using an LM358 and standard E12 components, contrast it with passive alternatives, and map out exactly what happens when components fail.
The Core Decision: Passive RC vs. Active Sallen-Key Circuit Filter
Choosing the right circuit filter topology comes down to source impedance, required roll-off steepness, and available board space. A passive RC filter is trivial to route, but its -20dB/decade slope means high-frequency noise (like a 50kHz PWM signal from a motor driver) will still bleed into the ESP32’s ADC sampling window. The Sallen-Key topology uses an operational amplifier to provide a -40dB/decade (second-order) roll-off while presenting a high input impedance and a low output impedance, effectively buffering the signal.
- IF your source impedance is < 100Ω, your signal is DC-dominant, and a gentle -20dB/decade roll-off is acceptable THEN use a Passive RC Filter (e.g., 100Ω and 1µF).
- IF your source impedance is > 1kΩ, you are sampling audio or fast-moving sensor data, and you must reject high-frequency aliasing THEN use an Active Sallen-Key Filter.
- IF you need > -40dB/decade THEN cascade two Sallen-Key stages or use a switched-capacitor IC.
Concrete Pick: For standard ESP32 ADC anti-aliasing where the Nyquist limit is practically around 4kHz–5kHz, a 2kHz unity-gain Sallen-Key circuit filter is the definitive bench standard.
Sallen-Key Topology: Node Labels and Behavior Matrix
To troubleshoot or modify this circuit filter on the bench, you must understand the node relationships. The unity-gain Sallen-Key low-pass topology consists of two resistors, two capacitors, and one op-amp configured as a voltage follower.
Node Definitions:
- VIN: The raw analog input signal.
- N1: The junction between R1, R2, and C1. (C1 routes from here to Ground).
- N2: The non-inverting input (+) of the op-amp. This is the junction between R2 and C2. (C2 routes from here to Ground).
- VOUT: The op-amp output, which is hard-wired back to the inverting input (-) to enforce unity gain (Buffer mode).
Understanding how component drift or substitution alters the transfer function is critical when you are forced to use non-ideal values from your parts bin.
| Element Changed | Impact on Cutoff Frequency ($f_c$) | Impact on Quality Factor ($Q$) / Peaking | Practical Consequence |
|---|---|---|---|
| Increase R1 or R2 | Decreases $f_c$ | Changes $Q$ (asymmetric shift) | Lowers the passband; alters the Butterworth flat response if only one is changed. |
| Increase C1 | Decreases $f_c$ | Increases $Q$ (causes peaking) | Passband remains, but a resonant peak forms just before the cutoff frequency. |
| Increase C2 | Decreases $f_c$ | Decreases $Q$ (overdamped) | Roll-off becomes sluggish; loses the sharp -40dB/decade knee, acting closer to two cascaded 1st-order filters. |
| Op-Amp Gain > 1 | Minimal shift | Dramatically increases $Q$ | Risks instability and oscillation if gain approaches 3.0. Stick to unity gain for robustness. |
Step-by-Step Design Walkthrough (2kHz Butterworth)
Let’s design a circuit filter with a target cutoff frequency ($f_c$) of 2000 Hz and a Butterworth response ($Q = 0.707$), which guarantees a maximally flat passband with no resonant peaking. For a unity-gain Sallen-Key topology, the math simplifies beautifully if we set $R_1 = R_2 = R$ and $C_1 = 2 \times C_2$.
1. Select the Capacitors:
Capacitor values dictate the physical size and dielectric behavior. We will pick $C_2 = 4.7\text{nF}$ and $C_1 = 10\text{nF}$. This gives a ratio of $10 / 4.7 = 2.12$, yielding a $Q$ of roughly $0.73$—close enough to the ideal $0.707$ for real-world anti-aliasing.
Critical E-E-A-T Note: You must use C0G/NP0 ceramic capacitors or film capacitors. Do not use X7R or Y5V dielectrics. X7R capacitors exhibit a severe Voltage Coefficient of Capacitance (VCC) and piezoelectric microphonics, which will distort your signal and shift your cutoff frequency as the signal amplitude changes.
2. Calculate the Resistors:
The cutoff frequency formula for this simplified topology is:
$f_c = \frac{1}{2 \pi R \sqrt{C_1 C_2}}$
Rearranging to solve for $R$:
$R = \frac{1}{2 \pi f_c \sqrt{C_1 C_2}}$
$R = \frac{1}{2 \pi (2000) \sqrt{(10 \times 10^{-9}) (4.7 \times 10^{-9})}}$
$R = \frac{1}{12566 \times 6.85 \times 10^{-9}} \approx 11,615\Omega$
3. Pick Standard Values:
The closest standard E12 resistor value is 10kΩ or 12kΩ. Let’s use 10kΩ 1% metal film resistors for low thermal noise. Recalculating the actual $f_c$ with 10kΩ yields approximately 2324 Hz, which perfectly protects an ESP32 ADC sampling at 5kHz or higher.
4. Select the Op-Amp:
For a 3.3V single-supply ESP32 system, a standard LM358 is acceptable for low-frequency sensor data, but its output cannot swing all the way to the 3.3V rail. For true rail-to-rail audio or precision sensor work, upgrade to an MCP6001 or TLV2371. We will specify the LM358P for this baseline BOM due to its ubiquity, but bias the input at 1.65V if measuring bipolar AC signals.
Failure Mode Analysis: What Breaks at the Extremes?
A major advantage of understanding circuit filter topology is predicting failure modes. Unlike a simple series/parallel passive network where a short might just blow a fuse, an active topology interacts with the op-amp's feedback loop. Here is the failure-mode contrast when extreme faults occur on the bench:
- C1 Shorts to Ground: The input signal at VIN is dragged directly to ground through R1. Result: VOUT drops to 0V (or the bias voltage). The preceding sensor stage may be overloaded if R1 is too small.
- C1 Opens: The path to ground at N1 is lost. The circuit degenerates into a 1st-order low-pass filter formed only by R2 and C2. Result: Roll-off degrades from -40dB/decade to -20dB/decade, allowing high-frequency aliasing to reach the ADC.
- C2 Shorts to Ground: The non-inverting input (N2) of the op-amp is pulled to ground. Result: VOUT locks to 0V (or the negative rail). The op-amp acts as a dead buffer.
- C2 Opens: The high-frequency feedback path to ground is broken. Result: The circuit loses its second-order filtering entirely and passes high frequencies directly through the op-amp’s open-loop gain bandwidth until the op-amp's internal slew-rate limits clip the signal.
- R2 Shorts: Nodes N1 and N2 merge. C1 and C2 are now effectively in parallel to ground. Result: The circuit becomes a 1st-order filter with a combined capacitance of 14.7nF, drastically lowering the cutoff frequency to roughly 1kHz with a very gradual slope.
Breadboard Testing and Verification Procedure
Do not trust SPICE simulations blindly; parasitic breadboard capacitance (typically 2pF–5pF per node) can shift a high-frequency circuit filter's response. Follow this numbered verification sequence to validate your physical build.
- Power and Bias: Connect VCC (3.3V or 5V) and GND to the LM358. Place a 100nF decoupling capacitor directly across the op-amp's power pins. If testing an AC signal, use a voltage divider (two 10kΩ resistors) to bias VIN at VCC/2.
- Inject the Sweep: Connect a function generator to VIN. Set it to output a 1Vpp sine wave. Start at 100 Hz.
- Verify Passband: Probe VOUT with an oscilloscope. At 100 Hz, VOUT should exactly match VIN (1Vpp). If it is attenuated, check for a miswired voltage divider or a damaged op-amp.
- Find the -3dB Point: Slowly increase the frequency. The -3dB cutoff occurs when the output amplitude drops to $0.707\text{Vpp}$ ($1\text{V} \times 0.707$). For our 10kΩ / 4.7nF / 10nF BOM, this should occur between 2.2 kHz and 2.4 kHz.
- Verify the Roll-off Slope: Increase the frequency to 10 kHz (roughly two octaves above the 2.3 kHz cutoff). A true second-order circuit filter will attenuate the signal by roughly -24dB from the passband peak. Your 1Vpp input should measure approximately 60mVpp at VOUT. If it measures closer to 200mVpp, C1 or C2 has failed open, and you are only seeing a 1st-order -20dB/decade slope.
- Check for Peaking: Sweep the frequency between 1.5 kHz and 2.5 kHz while watching the amplitude. If the voltage rises above 1Vpp before dropping off, your capacitor ratio is skewed, indicating a $Q > 0.707$. Swap the capacitors to verify their actual measured values with an LCR meter.
By standardizing on the 10kΩ / 4.7nF / 10nF Sallen-Key BOM with C0G dielectrics, you eliminate the guesswork from ESP32 analog front-end design. It provides a robust, easily sourced, and mathematically predictable circuit filter that guarantees clean ADC data on the first hardware spin.
