A logic gate circuit processes binary inputs to produce a single binary output. While integrated circuits like the 74HC02 CMOS NOR gate dominate modern designs for their microamp quiescent current and high fan-out, building a discrete Resistor-Transistor Logic (RTL) NOR gate on the bench remains the definitive way to understand node voltages, current steering, and failure modes. This guide walks through the exact component values, node behaviors, and fault extremes of an RTL topology, then contrasts it with modern CMOS implementations.
The RTL NOR Gate: Topology and Node Analysis
To understand how a logic gate circuit actually moves electrons, we start with a discrete RTL NOR gate. This topology uses NPN bipolar junction transistors (BJTs) as switches and resistors to steer current. It is the foundational building block of early space-age computing and remains the best educational model for visualizing logic states as physical voltages.
Design Walkthrough and Component Values
We will design a 2-input NOR gate powered by a 5.0V DC supply. The goal is to ensure the transistors switch cleanly between cutoff (open) and hard saturation (closed) without lingering in the active linear region, which causes slow propagation delays and excess heat.
- Q1, Q2: 2N3904 NPN transistors (general-purpose, high gain).
- R_B1, R_B2: 10 kΩ base resistors (limits base current, sets input impedance).
- R_C: 1 kΩ collector pull-up resistor (pulls output High when both transistors are off).
- V_CC: 5.0V regulated DC supply.
Node Labels:
- $V_{CC}$: 5V positive rail.
- $N_{IN-A}$, $N_{IN-B}$: Input nodes (driven to 5V or 0V).
- $N_{B1}$, $N_{B2}$: Base nodes of Q1 and Q2.
- $N_{C}$: Common collector node (tied to both Q1/Q2 collectors and R_C). This is our $V_{OUT}$.
- $N_{E}$: Common emitter node (tied to GND).
When $N_{IN-A}$ is driven to 5V, the base current $I_B$ is $(5.0V - 0.7V) / 10k\Omega = 0.43 mA$. If Q1 turns on, the maximum collector current $I_C$ is limited by $R_C$ to $(5.0V - 0.2V) / 1k\Omega = 4.8 mA$. The forced beta ($\beta_{forced}$) is $4.8 / 0.43 \approx 11$. Since a 2N3904 has a typical $\beta$ of 150, a forced beta of 11 guarantees the transistor is in deep saturation, pulling $N_C$ down to a solid 0.2V (Logic 0).
Behavior and Node Voltage Table
This table maps the logical inputs to the physical voltages you will measure on your multimeter at each critical node. This is the core behavior matrix for the RTL NOR topology.
| Input A | Input B | Q1 State | Q2 State | $N_{B1}$ (V) | $N_{B2}$ (V) | $N_C$ / V_OUT (V) | Logic Out |
|---|---|---|---|---|---|---|---|
| 0 (0V) | 0 (0V) | Cutoff | Cutoff | 0.00 | 0.00 | 5.00 | 1 (High) |
| 1 (5V) | 0 (0V) | Saturation | Cutoff | 0.70 | 0.00 | 0.20 | 0 (Low) |
| 0 (0V) | 1 (5V) | Cutoff | Saturation | 0.00 | 0.70 | 0.20 | 0 (Low) |
| 1 (5V) | 1 (5V) | Saturation | Saturation | 0.70 | 0.70 | 0.20 | 0 (Low) |
Failure Modes: What Breaks at the Extremes?
Abstract logic diagrams assume perfect components. On the bench, components fail, solder joints crack, and wires short. Understanding series/parallel failure modes in a logic gate circuit is critical for debugging.
Shorting a Base Resistor ($R_{B1}$)
If $R_{B1}$ shorts (or is bypassed by a solder bridge), the 5V rail connects directly to the base of Q1. The base-emitter junction acts like a forward-biased diode. Without the 10 kΩ resistor to limit current, $I_B$ will spike to hundreds of milliamps, limited only by the power supply's internal resistance and the PCB trace width. Result: Q1's base-emitter junction will overheat and fail open within seconds. Once open, Q1 becomes permanently unresponsive to Input A. If Input B is also Low, $N_C$ will float High, masking the failure until Input A is needed.
Opening the Collector Pull-Up ($R_C$)
If $R_C$ breaks or loses its connection to $V_{CC}$, the pull-up path is severed. Result: When either Q1 or Q2 turns on, $N_C$ is still pulled to GND (Logic 0). However, when both inputs are Low, both transistors are off. With no pull-up resistor, the $N_C$ node is left floating. A digital multimeter will read random, drifting millivolts, and an oscilloscope will show the node picking up 50/60Hz mains hum from the environment. The logic gate loses its ability to output a Logic 1.
Shorting Q1 Collector-to-Emitter
If Q1 suffers a catastrophic die short between collector and emitter (often caused by exceeding $V_{CEO}$ or excessive power dissipation), $N_C$ becomes hard-tied to GND. Result: The output is permanently stuck at Logic 0 (approx 0.0V), regardless of the states of Input A or Input B. This is a 'stuck-at-0' fault that will cascade and lock up any downstream logic relying on this gate.
Why CMOS (74HC02) Wins Over Discrete RTL
While RTL is brilliant for learning, no one builds discrete RTL logic gate circuits for production in 2026. Modern designs use Complementary Metal-Oxide-Semiconductor (CMOS) logic, like the Texas Instruments SN74HC02 quad 2-input NOR gate. The fundamental difference lies in how the output is pulled High.
In our RTL design, pulling $N_C$ High relies on current flowing continuously through $R_C$ into the load. In a CMOS gate, the pull-up resistor is replaced by a network of P-channel MOSFETs. When the output needs to be High, the PMOS transistors turn on, creating a near-zero-resistance path to $V_{CC}$. When the output needs to be Low, the PMOS turns off and an N-channel MOSFET network pulls the output to GND. Because one network is always completely off in a steady state, the static current draw is virtually zero.
| Parameter | Discrete RTL NOR (2N3904) | CMOS 74HC02 NOR Gate | Why CMOS Wins |
|---|---|---|---|
| Quiescent Current (Idle) | 0 mA (but draws 5mA when outputting Low) | < 2 µA per package | CMOS enables battery-powered logic for years; RTL drains batteries in hours. |
| Input Impedance | ~10 kΩ (set by base resistors) | > 100 GΩ (MOSFET gate oxide) | CMOS doesn't load down the previous stage, allowing massive fan-out. |
| Logic Fan-Out | 4 to 5 standard TTL/RTL loads | > 1,000 CMOS inputs | CMOS inputs draw only picoamps of leakage current. |
| Propagation Delay ($t_{pd}$) | ~100 ns (limited by BJT charge storage) | ~15 ns (at 5V, 50pF load) | CMOS switches faster without the BJT saturation delay penalty. |
| Component Count | 5 discrete parts per gate | 4 gates in a single 14-pin IC | CMOS drastically reduces board space, parasitic inductance, and assembly cost. |
For a deep dive into the internal transistor-level schematics of modern CMOS gates, the ON Semi MC74HC02 Datasheet provides excellent cross-sectional diagrams of the P-well and N-well structures that make this efficiency possible.
Breadboard Testing: Step-by-Step Verification
Whether you are validating a discrete RTL prototype or testing a salvaged 74HC02 IC, a systematic breadboard verification sequence prevents blown ICs and misdiagnosed faults. Follow this exact sequence.
Step 1: Unpowered Continuity and Short Checks
Before applying power, set your digital multimeter (DMM) to continuity mode. Place the black probe on the GND rail and the red probe on the $V_{CC}$ rail. You should read an open circuit (OL) or a very high resistance. If it beeps, you have a dead short—likely a misaligned IC or a solder bridge. Fix it before proceeding.
Step 2: Power Rail Verification
Turn on your bench power supply. Set it to 5.00V. Do not rely on the supply's digital readout; measure the breadboard rails directly with your DMM. A reading between 4.95V and 5.05V is acceptable. If you are testing a 74HC series IC, exceeding 6.0V will permanently rupture the gate oxide.
Step 3: Static Logic State Testing
For the RTL circuit, use jumper wires to tie $N_{IN-A}$ and $N_{IN-B}$ to either GND (Logic 0) or $V_{CC}$ (Logic 1).
- Tie both to GND. Measure $N_C$ with the DMM. It must read > 4.5V.
- Tie A to $V_{CC}$, B to GND. Measure $N_C$. It must read < 0.3V.
Step 4: Dynamic Edge and Propagation Delay Test
Static tests miss timing hazards. To measure propagation delay, connect a function generator (or a 555 timer astable circuit) to Input A, set to a 100 kHz square wave (0V to 5V). Tie Input B to GND. Connect Channel 1 of your oscilloscope to Input A, and Channel 2 to $N_C$. Trigger on the rising edge of Channel 1. Measure the time delta between the 50% voltage point of the input rising edge and the 50% voltage point of the output falling edge. For a discrete RTL gate, expect a delay of 50ns to 150ns due to the BJT turn-off storage time. For a 74HC02, this delta should be under 20ns.
By mastering both the raw physics of the discrete RTL topology and the engineered efficiency of CMOS, you bridge the gap between abstract Boolean algebra and the physical reality of electrons moving through silicon.
