The resonant frequency of an RLC circuit is determined exclusively by the inductor (L) and capacitor (C) values according to the formula fr = 1 / (2π√LC). The resistor (R) does not shift this center frequency; instead, it dictates the Quality factor (Q) and the bandwidth of the resonance peak. If you are designing a bandpass filter, an antenna matching network, or an oscillator tank, your first critical decision is choosing between a series or parallel topology. This choice defines whether your circuit presents a low or high impedance at resonance, which in turn determines how it interfaces with your source and load.
The Core Decision: Series vs. Parallel RLC Topologies
Before picking component values, you must define the signal path. The two fundamental topologies behave as exact duals of one another at resonance.
Series RLC (Bandpass / Low Impedance)
In a series topology, components are daisy-chained. Signal enters at Node A (Vin), passes through the resistor to Node B, through the inductor to Node C, and through the capacitor to Node D (GND). The output (Vout) is typically taken across the capacitor (Node C to Node D). At the resonant frequency, the inductive and capacitive reactances cancel out (XL = XC). The circuit's impedance drops to just the resistance (R), allowing maximum current to flow and creating a voltage peak across the capacitor. Use this when you need to pass a specific frequency to a low-impedance load.
Parallel RLC (Bandstop / High Impedance Tank)
In a parallel topology, the inductor, capacitor, and resistor all share the same two nodes. Node A (Vin) splits into three parallel branches, which all recombine at Node B (GND). At resonance, the LC tank presents a theoretically infinite impedance (limited only by parasitic resistance). Use this topology when you need to block a specific frequency (notch filter) or when driving a high-impedance load like a MOSFET gate or an op-amp buffer.
For most bench-level signal conditioning (e.g., isolating a 100 kHz carrier from broadband noise), the series RLC is the superior default. It is driven easily by standard 50 Ω function generators, requires no active buffering to prevent load-impedance detuning, and provides a clean, predictable bandpass response. Parallel tanks are notoriously difficult to tune on a breadboard because the input impedance of your oscilloscope probe (typically 1 MΩ || 15 pF) directly loads the tank, collapsing the Q factor and shifting the resonant frequency.
Design Walkthrough: Targeting 100 kHz with Real Components
Let’s design a series RLC bandpass filter targeting a resonant frequency of RLC circuit at exactly 100 kHz. We will select off-the-shelf, through-hole components available from standard distributors like Digi-Key or Mouser.
1. Select the Inductor (L):
We need an inductor with a self-resonant frequency (SRF) well above 100 kHz to avoid parasitic capacitance ruining our math. A 1 mH inductor is a solid bench choice.
Pick: Bourns 78F1R0K-RC (1 mH, ±10%, DCR = 1.4 Ω, SRF = 1.1 MHz). Cost: ~$0.45.
2. Calculate and Select the Capacitor (C):
Rearranging the resonance formula: C = 1 / ((2πfr)² × L).
C = 1 / ((2π × 100,000)² × 0.001) = 2.533 nF.
Standard E12/E24 capacitor values won't hit this exactly. To get precision, we parallel two C0G/NP0 dielectric capacitors (C0G is mandatory here; X7R dielectrics exhibit severe capacitance loss and microphonics at AC voltages).
Pick: 2.2 nF (Kemet C315C222J1G5TA) + 330 pF (Kemet C315C331J1G5TA) in parallel. Total C = 2.53 nF. Cost: ~$0.20 total.
3. Select the Resistor (R) for Target Q:
The Q factor determines the bandwidth (BW = fr / Q). For a series circuit, Q = (1/R) × √(L/C).
If we want a moderately sharp filter (Q ≈ 13, yielding a ~7.6 kHz bandwidth), we solve for R: R = √(L/C) / Q.
R = √(0.001 / 2.53e-9) / 13 ≈ 48.4 Ω.
Accounting for the inductor's 1.4 Ω DCR, we need an external resistor of roughly 47 Ω.
Pick: Yageo CFR-25JB-52-47R (47 Ω, 1/4W carbon film). Cost: ~$0.05.
Behavior Matrix and Failure Mode Contrast
Understanding how component drift affects the circuit is critical for troubleshooting. Here is the behavior matrix for our 100 kHz series design.
| Component Change | Effect on Resonant Frequency (fr) | Effect on Q Factor / Bandwidth | Real-World Cause |
|---|---|---|---|
| Inductance (L) Increases | Decreases | Increases Q (narrower BW) | Core saturation, temperature drift in ferrite |
| Capacitance (C) Increases | Decreases | Decreases Q (wider BW) | Dielectric absorption, thermal expansion |
| Resistance (R) Increases | No Change | Decreases Q (wider BW, lower peak) | Resistor heating, poor breadboard contact |
What Breaks at the Extremes?
When debugging a dead circuit, you must know how hard failures manifest in both topologies.
- Series RLC - Capacitor Shorts: Vout drops to 0V DC. The inductor and resistor simply act as a low-value current limiter to ground. The function generator may fold back or overheat if not 50 Ω protected.
- Series RLC - Inductor Opens: Vout drops to 0V. The circuit is broken; no AC current can flow regardless of frequency.
- Parallel RLC - Capacitor Shorts: Vout drops to 0V. The tank is destroyed, and the source sees a dead short through the parallel resistor.
- Parallel RLC - Inductor Opens: The circuit ceases to be a resonant tank and degrades into a simple first-order RC low-pass filter. You will see signal at low frequencies, but the sharp resonance peak vanishes entirely.
Breadboard Verification: Step-by-Step Testing Protocol
Theory assumes ideal components; the breadboard introduces parasitics. Adjacent rows on a standard solderless breadboard introduce ~2 pF to 5 pF of stray capacitance. At 100 kHz, this is negligible (XC > 300 kΩ), but poor wiring practices will still ruin your Q factor. Follow this exact protocol using a standard AC resonance testing methodology.
- Configure the Source: Set your function generator (e.g., Siglent SDG1032X) to a Sine wave, 1.0 Vpp, 100 kHz. Critical: Set the output impedance mode to 50 Ω. If left on High-Z, the generator's physical 50 Ω output resistor will form an unintended voltage divider with your circuit, halving your expected amplitude.
- Wire the Circuit: Insert the Bourns inductor, Kemet capacitors, and Yageo resistor in series. Keep component leads as short as possible. Do not bridge the capacitor across multiple distant breadboard rows to avoid adding stray parallel capacitance.
- Probe the Output: Connect a 10x passive oscilloscope probe across the capacitor (Node C to GND). Verify: Ensure the probe compensation capacitor is tuned using the scope's square wave calibrator. An under-compensated 10x probe will artificially attenuate high frequencies and skew your bandwidth readings.
- Sweep the Frequency: Use the generator's sweep function or manually step from 80 kHz to 120 kHz in 1 kHz increments. Record the Vpp at each step.
- Identify the Peak: You should see a voltage magnification. With a Q of ~13, the voltage across the capacitor at 100 kHz should peak at roughly Q × Vin (minus resistive losses), yielding approximately 10 Vpp to 12 Vpp from a 1 Vpp input.
- Measure Bandwidth: Find the two frequencies where the voltage drops to 70.7% (-3 dB) of the peak voltage. The difference between these two frequencies is your -3 dB bandwidth. It should measure close to 7.6 kHz.
If your oscilloscope shows a flattened or distorted sine wave at the resonant peak, your inductor core is saturating. The 1mH Bourns part listed above is rated for roughly 160 mA DC. At resonance, the Q-magnified voltage across the inductor can drive AC currents that exceed this limit, causing the inductance to plummet and the resonant frequency to dynamically shift upward as amplitude increases. If you see this, drop the function generator amplitude to 0.2 Vpp and scale your measurements.
Decision Tree: Final Topology and Component Selection
Do not default to a parallel tank simply because it is heavily featured in RF textbook oscillator chapters. Use this decision matrix to lock in your topology and parts for your specific application.
| Application Constraint | Required Topology | Component Selection Strategy |
|---|---|---|
| Driving a 50 Ω coaxial cable or ADC input | Series RLC | Match external R to 50 Ω; use C0G caps to prevent microphonic noise. |
| Driving a high-Z MOSFET gate or Op-Amp | Parallel RLC | Use high-Q air-core inductors; buffer the output with a unity-gain op-amp to prevent probe loading. |
| Need to reject a specific interference frequency | Parallel RLC (in series with signal path) | Place the parallel tank in series with the signal line; it acts as a high-impedance notch filter at fr. |
| Audio crossover or low-frequency sub-10 kHz filtering | Series RLC | Use large electrolytic caps (bipolar) and iron-core inductors; accept lower Q due to high ESR. |
The Default Recommendation
If you are building a general-purpose IF (intermediate frequency) filter, an RFID antenna matching prototype, or simply need a reliable bandpass filter for bench testing, build the Series RLC. It is vastly more forgiving of breadboard parasitics and oscilloscope probe loading.
For a 100 kHz center frequency, procure the Bourns 78F1R0K-RC (1 mH), parallel a 2.2 nF and 330 pF C0G capacitor, and terminate with a 47 Ω carbon film resistor. This exact bill of materials will yield a stable, predictable 100 kHz resonant peak with a ~7.6 kHz bandwidth, providing a robust foundation for any AC resonant circuit analysis or sensor interface project you undertake.
