The Problem Statement and Component Specifications

Exam Problem: A 24V DC ideal voltage source is connected via a switch to a resistor network. Resistor R1 (4 kΩ) is in series with the source. Resistor R2 (6 kΩ) is connected from the other end of R1 to ground. A capacitor C (470 μF) is placed in parallel with R2. The capacitor is fully discharged at t < 0. The switch closes at t = 0. Calculate the exact voltage across the capacitor, Vc(t), at t = 2.5 seconds.

Before touching the algebra, we map the charging curve. In any resistor capacitor circuit example, pre-calculating the time constant (τ) milestones saves you from careless arithmetic errors during an exam and provides an immediate sanity check for your final answer. Based on the Thevenin equivalent of this specific network (which we will derive below), the final voltage is 14.4V and τ is 1.128 seconds.

Table 1: RC Charging Milestones (Vfinal = 14.4V, τ = 1.128s)
Time (t) Multiples of τ Theoretical Vc % of Vfinal
0.000 s 0τ 0.00 V 0.0%
1.128 s 1τ 9.10 V 63.2%
2.256 s 2τ 12.45 V 86.5%
3.384 s 3τ 13.68 V 95.0%
4.512 s 4τ 14.14 V 98.2%
5.640 s 5τ 14.30 V 99.3%

Method Selection and the Classic Exam Trap

Which method applies and why? You must use Thevenin's Theorem. The universal time constant formula for an RC circuit requires a simple series loop consisting of one equivalent voltage source, one equivalent resistance, and the capacitor. Because R1 and R2 form a voltage divider relative to the capacitor's terminals, the capacitor does not "see" the raw 24V source, nor does it charge through the simple sum of the two resistors.

⚠ The Trap: The most common mistake in this specific resistor capacitor circuit example is assuming Vfinal = 24V and τ = (R1 + R2) × C. Students who fall for this trap calculate τ = 10 kΩ × 470 μF = 4.7s, leading to a drastically incorrect final voltage. The capacitor only charges to the open-circuit voltage at its terminals, and it charges at a rate dictated by the equivalent resistance looking back into the network with the voltage source zeroed (shorted).

Step-by-Step Algebraic Solution

We will break the solution down into four distinct phases, showing every algebraic manipulation.

Step 1: Find the Thevenin Voltage (Vth)

Remove the capacitor to create an open circuit. Calculate the voltage across the open terminals (which is the voltage across R2).

  • Vth = Vsource × [ R2 / (R1 + R2) ]
  • Vth = 24V × [ 6 kΩ / (4 kΩ + 6 kΩ) ]
  • Vth = 24V × (6 / 10)
  • Vth = 14.4 V (This is our Vfinal)

Step 2: Find the Thevenin Resistance (Rth)

Zero the independent voltage source (replace the 24V source with a short circuit). Look back into the terminals where the capacitor was connected. R1 and R2 are now in parallel.

  • Rth = (R1 × R2) / (R1 + R2)
  • Rth = (4 kΩ × 6 kΩ) / (4 kΩ + 6 kΩ)
  • Rth = 24 / 10 kΩ
  • Rth = 2.4 kΩ = 2400 Ω

Step 3: Calculate the Time Constant (τ)

Multiply the Thevenin resistance by the capacitance. Ensure units are in base SI (Ohms and Farads).

  • τ = Rth × C
  • τ = 2400 Ω × 470 × 10-6 F
  • τ = 2400 × 0.000470
  • τ = 1.128 seconds

Step 4: Apply the Universal Time Constant Formula

The formula for charging is: Vc(t) = Vfinal + (Vinitial - Vfinal)e-t/τ. Since the capacitor starts fully discharged, Vinitial = 0V, simplifying the equation to Vc(t) = Vfinal(1 - e-t/τ).

  • Vc(2.5) = 14.4 × (1 - e-2.5 / 1.128)
  • Calculate the exponent: -2.5 / 1.128 = -2.216312
  • Calculate Euler's number to that power: e-2.216312 ≈ 0.108965
  • Subtract from 1: 1 - 0.108965 = 0.891035
  • Multiply by Vfinal: 14.4 × 0.891035 = 12.8309
  • Final Answer: Vc(2.5s) = 12.83 V

Sanity Checks and Independent Verification

Never hand in an exam paper or finalize a PCB design without a sanity check.

Order of Magnitude and Bounds Check: Look back at Table 1. Our target time (2.5s) is slightly greater than 2τ (2.256s) but well below 3τ (3.384s). At 2τ, the voltage is 12.45V. At 3τ, it is 13.68V. Our calculated answer of 12.83V falls perfectly within this boundary, sitting just above the 2τ mark. The units are strictly in Volts, and the magnitude makes physical sense for a 24V source divided by a 4k/6k network.

How to verify the answer independently:

  1. SPICE Simulation: Build the netlist in LTspice XVII. Use a PULSE voltage source configured to step from 0V to 24V at t=0. Run a transient analysis command (.tran 6) and probe the node between R1 and R2. Place a cursor at exactly t=2.5s; the simulation will read 12.8309V, confirming the hand math.
  2. Bench Verification: Build the physical circuit using 1% tolerance metal film resistors (e.g., Vishay MRS25 series) and a high-quality film capacitor (avoid cheap electrolytics which can have -20%/+80% capacitance tolerance and high ESR). Use a digital multimeter with a min/max or logging function, like the Fluke 87V Series V, to capture the voltage at the 2.5-second mark. Account for a ±2% deviation due to real-world component tolerances.

Frequently Asked Questions

Q: What if the switch opens at t = 2.5s instead of closing?
A: If the circuit was at steady state and the switch opens, you must redraw the circuit for the discharging phase. The capacitor will discharge through whatever closed loop remains. If R1 is disconnected, it discharges solely through R2, meaning the new τ would be R2 × C (6000 × 470μF = 2.82s).

Q: Does the internal resistance of the 24V source matter?
A: In textbook problems, sources are ideal (0 Ω internal resistance). In a physical lab setting, a bench power supply might have 50 mΩ of output impedance. Because 50 mΩ is negligibly small compared to 4 kΩ, it is safely ignored in both the exam and the physical prototype.

References: For deeper reading on RC transient mathematics and Thevenin equivalents, consult the All About Circuits RC Time Constants chapter and the Electronics Tutorials RC Charging Circuit guide.