The direct answer for thermal designers: the resistivity temperature coefficient (TCR or α) is the fractional change in a material's electrical resistance per degree of temperature change. For most conductors (copper, aluminum) and silicon power devices, TCR is positive. As your components heat up, their resistance increases, which drives up I²R power dissipation. If your heatsink is sized only for room-temperature resistance, this positive feedback loop will push your junction temperatures past safe limits, triggering thermal runaway.
In this guide, we will walk through the junction-to-ambient thermal math, interpret silicon derating curves, and select a real-world heatsink using actual wattage figures that account for temperature-induced resistance shifts.
The Math: Junction-to-Ambient Thermal Paths and TCR
To manage heat, you must first calculate the thermal path from the silicon junction to the ambient air. The foundational equation is:
T_J = T_A + (P_D × θ_JA)
Where T_J is junction temperature, T_A is ambient temperature, P_D is power dissipation, and θ_JA is the total thermal resistance (junction-to-ambient) in °C/W.
The trap most beginners fall into is treating P_D as a static number. Because of the resistivity temperature coefficient, P_D scales with temperature. For a copper PCB trace, the linear TCR (α) is approximately +0.00393 /°C. A 50°C temperature rise increases trace resistance by nearly 20%, directly increasing I²R heating.
For silicon MOSFETs, the channel resistance (R_DS(on)) doesn't follow a simple linear α. Instead, datasheets provide a normalized derating curve. Let's look at a practical example using a standard N-channel MOSFET like the IRF3205:
- Baseline: At 25°C,
R_DS(on)is 8 mΩ. At 20A continuous,P_D= 20² × 0.008 = 3.2W. - At Temperature: The derating curve shows a multiplier of ~1.6 at 100°C. The hot
R_DS(on)becomes 12.8 mΩ. At 20A,P_D= 20² × 0.0128 = 5.12W.
If you size your heatsink for 3.2W, the junction will run hotter than expected. That higher temperature increases
R_DS(on) further, which increases wattage, which increases temperature. Without sufficient thermal headroom, this positive TCR feedback loop ends in a melted package or catastrophic silicon failure.
Heatsink Selection: A Real-World Wattage Basis
Let's select a heatsink for the 5.12W hot-dissipation scenario above. We want to keep the MOSFET junction (T_J) under 100°C for long-term reliability, assuming an enclosure ambient (T_A) of 40°C.
First, find the maximum allowable total thermal resistance:
θ_JA(max) = (100°C - 40°C) / 5.12W = 11.7 °C/W
Next, we break θ_JA down into its series components: θ_JC (junction-to-case), θ_CS (case-to-sink), and θ_SA (sink-to-ambient).
| Thermal Interface | Symbol | Value (°C/W) | Notes / Material |
|---|---|---|---|
| Junction-to-Case | θ_JC |
1.5 | Fixed by MOSFET die/package (TO-220) |
| Case-to-Sink | θ_CS |
0.5 | Using Bergquist Sil-Pad 900 thermal pad |
| Sink-to-Ambient | θ_SA |
? | The heatsink we need to select |
Subtracting the known resistances from our total budget:
θ_SA(max) = 11.7 - 1.5 - 0.5 = 9.7 °C/W
For a natural convection (passive) TO-220 application, the Aavid Thermalloy 577102B00000G is an excellent choice. It features a black anodized finish for better emissivity and a rated θ_SA of roughly 8.5 °C/W in still air. Because 8.5 °C/W is less than our 9.7 °C/W maximum, this heatsink provides the necessary margin to absorb the wattage increase caused by the silicon's positive resistivity temperature coefficient.
Failure Signatures: How Hot is Too Hot?
Silicon dies typically shut down or destruct at 150°C to 175°C, but running anywhere near those limits is a mistake. How hot is too hot? For long-term reliability, keep T_J below 100°C. According to the Arrhenius equation, the operational lifespan of surrounding components (like electrolytic capacitors) halves for every 10°C rise in ambient temperature.
Failure Signatures of Thermal Stress
When TCR-driven thermal runaway or chronic overheating occurs, you will see specific physical signatures on the bench:
- Solder Joint Creep and Cracking: Repeated thermal cycling causes the solder to yield. Look for micro-cracks around the MOSFET leads or heavy DPAK pads.
- PCB Delamination: If the local board temperature exceeds the FR-4 glass transition temperature (
T_g, typically 130°C to 170°C), the resin softens, causing the copper layers to delaminate and vias to barrel-crack. - Gate Oxide Breakdown: High junction temperatures accelerate time-dependent dielectric breakdown (TDDB) in the MOSFET's thin gate oxide, leading to sudden, short-circuit failures between gate and source.
What Airflow and Enclosure Changes Buy You
If your passive heatsink math fails due to space constraints, forced convection alters the θ_SA dramatically. Here is what specific changes buy you:
| Cooling Intervention | Impact on θ_SA | Practical Implementation |
|---|---|---|
| Passive (Still Air) | Baseline | Requires large fin surface area and vertical mounting. |
| Low Airflow (1 m/s) | Reduces θ_SA by ~40% | Adding a 40mm fan (e.g., Noctua NF-A4x20) pushing air across fins. |
| Enclosure Louvers | Drops local T_A by 10-15°C | Cutting bottom intake and top exhaust vents to establish a chimney effect. |
Frequently Asked Questions
Does the resistivity temperature coefficient affect PCB copper trace sizing?
Yes, significantly. Standard trace width calculators (like the IPC-2221 based tools) often default to a 20°C or 30°C temperature rise. Because copper has a positive TCR of +0.00393 /°C, a trace designed for a 40°C rise will have roughly 15% higher resistance at operating temperature than at room temperature. This means the actual I²R heating will be higher than the calculator's baseline assumption. For high-current paths (e.g., >10A), always use 2 oz copper and add thermal vias to inner ground planes to act as a heatsink, keeping the trace temperature rise below 20°C to minimize TCR-induced resistance penalties.
How do I calculate power loss using the resistivity temperature coefficient for a shunt resistor?
Current sense shunt resistors are specifically manufactured to have an extremely low TCR, often rated in parts per million per degree Celsius (ppm/°C). For example, a Bourns CSS 2512 shunt might have a TCR of ±50 ppm/°C (which is 0.00005 /°C). To calculate hot power loss: R_hot = R_nominal × [1 + (TCR × ΔT)]. If your 1 mΩ shunt heats up by 50°C, the resistance shifts to 1.0025 mΩ. The power loss at 30A goes from 0.900W to 0.902W. While the absolute wattage change is tiny, the TCR-induced resistance shift is critical for measurement accuracy, which is why precision shunts use alloys like Manganin or Evanohm rather than pure copper.
Are there materials with a negative resistivity temperature coefficient for thermal management?
Yes. Semiconductors, thermistors (specifically NTC types), and carbon exhibit a negative resistivity temperature coefficient. As they heat up, their resistance drops. In thermal management, NTC thermistors are deliberately used as inrush current limiters (NTC ICLs). When cold, their high resistance limits the surge current into capacitive loads. As current flows, they self-heat, their resistance plummets due to the negative TCR, and they step out of the way to minimize steady-state power loss. However, you must be careful: if an NTC device is used in a standard biasing circuit without current limiting, the negative TCR can cause its own form of thermal runaway, drawing more current as it gets hotter until it destroys itself.
